[PATCH v2] drm/i915/mtl: Update workaround 14018778641

[Andi Shyti]

Hi Angus,

On Mon, May 13, 2024 at 02:19:17PM +0000, Chen, Angus wrote:
> The WA should be extended to cover VDBOX engine. We found that
> 28-channels 1080p VP9 encoding may hit this issue.
> 
> Signed-off-by: Chen, Angus <angus.chen at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d1ab560fcdfc..da0a481a375e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1586,6 +1586,9 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  	 */
>  	wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
>  
> +	/* Wa_14018778641 */
> +	wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);

Wa_14018778641 says that we need to disable the FTLB for Compute,
Render, GSC, VDBox and VEBox engines, but here we are doing it
only for GSC and VDBox, why?

Besides, in MTL we have the media GT where the MOD_CTRL family
has address 0x38cf34. Should this be checked and included, as
well?

Thanks,
Andi

>  	/* Wa_22016670082 */
>  	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>  
> -- 
> 2.34.1