[PATCH] drm/i915: Fix SEL_FETCH_{SIZE,OFFSET} registers

Jani Nikula jani.nikula at intel.com
Mon May 27 07:37:43 UTC 2024


On Fri, 24 May 2024, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Fix up the SEL_FETCH_{SIZE,OFFSET} registers. A classic
> copy-paste fail on my part.
>
> I even had a small test to confirm that the old and new register
> offsets match, but somehow I must have screwed things up when
> running it, and likely just ended up comparing the old defines
> against themselves :/
>
> Cc: Jani Nikula <jani.nikula at intel.com>
> Fixes: 4bfa8a140db3 ("drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()")
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Ugh. And here I thought I did a pretty thorough job reviewing that
series. :(

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  .../drm/i915/display/skl_universal_plane_regs.h  | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 9904ecc54128..4ddcd7d46bbd 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -419,10 +419,10 @@
>  #define _SEL_FETCH_PLANE_SIZE_5_B		0x71928
>  #define _SEL_FETCH_PLANE_SIZE_6_B		0x71948
>  #define SEL_FETCH_PLANE_SIZE(pipe, plane)	_MMIO_SEL_FETCH((pipe), (plane),\
> -								_SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
> -								_SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
> -								_SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
> -								_SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
> +								_SEL_FETCH_PLANE_SIZE_1_A, _SEL_FETCH_PLANE_SIZE_1_B, \
> +								_SEL_FETCH_PLANE_SIZE_2_A, _SEL_FETCH_PLANE_SIZE_2_B, \
> +								_SEL_FETCH_PLANE_SIZE_5_A, _SEL_FETCH_PLANE_SIZE_5_B, \
> +								_SEL_FETCH_PLANE_SIZE_6_A, _SEL_FETCH_PLANE_SIZE_6_B)
>  
>  /* tgl+ */
>  #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089c
> @@ -434,9 +434,9 @@
>  #define _SEL_FETCH_PLANE_OFFSET_5_B		0x7192c
>  #define _SEL_FETCH_PLANE_OFFSET_6_B		0x7194c
>  #define SEL_FETCH_PLANE_OFFSET(pipe, plane)	_MMIO_SEL_FETCH((pipe), (plane),\
> -								_SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
> -								_SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
> -								_SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
> -								_SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
> +								_SEL_FETCH_PLANE_OFFSET_1_A, _SEL_FETCH_PLANE_OFFSET_1_B, \
> +								_SEL_FETCH_PLANE_OFFSET_2_A, _SEL_FETCH_PLANE_OFFSET_2_B, \
> +								_SEL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \
> +								_SEL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B)
>  
>  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */

-- 
Jani Nikula, Intel


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