[PATCH] drm/i915/dp_mst: Fix dsc mst bw overhead calculation

[Imre Deak]

On Wed, Oct 09, 2024 at 11:10:50AM +0530, Suraj Kandpal wrote:
> Fix the DSC flag assignment based on the dsc_slice_count returned
> to avoid divide by zero error.
> 
> Fixes: 4e0837a8d00a ("drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation")
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 4765bda154c1..bacd294d6bb6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -105,11 +105,16 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
>  	if (dsc) {
>  		int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
>  
> -		flags |= DRM_DP_BW_OVERHEAD_DSC;
>  		dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
>  							       adjusted_mode->clock,
>  							       adjusted_mode->hdisplay,
>  							       num_joined_pipes);
> +		/*
> +		 * Try with dsc only if dsc_slice_count has a sane value i.e value is no
> +		 * 0
> +		 */
> +		if (dsc_slice_count)
> +			flags |= DRM_DP_BW_OVERHEAD_DSC;

This would enable DSC, but with the wrong BW alloced. We'd need instead:
https://lore.kernel.org/all/20241009110135.1216498-1-imre.deak@intel.com

>  	}
>  
>  	overhead = drm_dp_bw_overhead(crtc_state->lane_count,
> -- 
> 2.43.2
>