[PATCH v2 11/12] drm/i915/xe3lpd: Skip disabling VRR during modeset disable

Golani, Mitulkumar Ajitkumar mitulkumar.ajitkumar.golani at intel.com
Thu Oct 24 17:24:45 UTC 2024



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Clint
> Taylor
> Sent: 24 October 2024 03:17
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Subject: [PATCH v2 11/12] drm/i915/xe3lpd: Skip disabling VRR during
> modeset disable
> 
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli at intel.com>
> 
> Spec does not request to disable VRR in the modeset disabling sequence for
> DP and HDMI for xe3_lpd.
> 
> Bspec: 68848
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli at intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 124e094a9999..bc35327b37d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1310,9 +1310,11 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	enum pipe pipe = crtc->pipe;
> 
> -	if (intel_crtc_vrr_disabling(state, crtc)) {
> -		intel_vrr_disable(old_crtc_state);
> -		intel_crtc_update_active_timings(old_crtc_state, false);
> +	if (DISPLAY_VER(dev_priv) < 30) {
> +		if (intel_crtc_vrr_disabling(state, crtc)) {
> +			intel_vrr_disable(old_crtc_state);
> +

in current implementation as we are still depending on legacy timing generator,
what if crtc_state.vrr.enable transitioned from enable to disable ? 

I think this also needs to be added along vrr default timing generator patch series. 

			intel_crtc_update_active_timings(old_crtc_state,
> false);
> +		}
>  	}
> 
>  	if (audio_disabling(old_crtc_state, new_crtc_state))
> --
> 2.25.1



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