[PATCH v5 06/11] drm/i915/cx0: Remove bus reset after every c10 transaction

[Gustavo Sousa]

Quoting Clint Taylor (2024-10-25 17:47:38-03:00)
>C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
>transaction. Starting with xe3lpd this is bus reset not necessary

I provided a r-b with minor suggestions to this patch in the v4 series:

https://lore.kernel.org/intel-xe/172986437914.1548.2518455286416273948@gjsousa-mobl2/

--
Gustavo Sousa

>
>Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 4d6e1c135bdc..c6e0cbff5201 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -224,7 +224,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
>          * down and let the message bus to end up
>          * in a known state
>          */
>-        intel_cx0_bus_reset(encoder, lane);
>+        if (DISPLAY_VER(i915) < 30)
>+                intel_cx0_bus_reset(encoder, lane);
> 
>         return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
> }
>@@ -313,7 +314,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
>          * down and let the message bus to end up
>          * in a known state
>          */
>-        intel_cx0_bus_reset(encoder, lane);
>+        if (DISPLAY_VER(i915) < 30)
>+                intel_cx0_bus_reset(encoder, lane);
> 
>         return 0;
> }
>-- 
>2.25.1
>