[PATCH 02/11] drm/i915/cdclk: Extract intel_cdclk_guardband() and intel_cdclk_ppc()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> We are duplicating the CDCLK guardband and "pixels per clock"
> figures in two places. Pull those out into small helpers that
> can be used by both places.

Oh, it's not just that, it's great to untangle the conflated two things!

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 50 +++++++++++-----------
>  1 file changed, 26 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6cef3ca3a069..977fcdaa7372 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2761,23 +2761,34 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  			"Post changing CDCLK to");
>  }
>  
> +/* pixels per CDCLK */
> +static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
> +{
> +	return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
> +}
> +
> +/* max pixel rate as % of CDCLK (not accounting for PPC) */
> +static int intel_cdclk_guardband(struct intel_display *display)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> +	if (DISPLAY_VER(display) >= 9 ||
> +	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> +		return 100;
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		return 95;
> +	else
> +		return 90;
> +}
> +
>  static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
> +	int guardband = intel_cdclk_guardband(display);
>  	int pixel_rate = crtc_state->pixel_rate;
>  
> -	if (DISPLAY_VER(display) >= 10)
> -		return DIV_ROUND_UP(pixel_rate, 2);
> -	else if (DISPLAY_VER(display) == 9 ||
> -		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -		return pixel_rate;
> -	else if (IS_CHERRYVIEW(dev_priv))
> -		return DIV_ROUND_UP(pixel_rate * 100, 95);
> -	else if (crtc_state->double_wide)
> -		return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
> -	else
> -		return DIV_ROUND_UP(pixel_rate * 100, 90);
> +	return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
>  }
>  
>  static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
> @@ -3452,20 +3463,11 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>  
>  static int intel_compute_max_dotclk(struct intel_display *display)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +	int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
> +	int guardband = intel_cdclk_guardband(display);
>  	int max_cdclk_freq = display->cdclk.max_cdclk_freq;
>  
> -	if (DISPLAY_VER(display) >= 10)
> -		return 2 * max_cdclk_freq;
> -	else if (DISPLAY_VER(display) == 9 ||
> -		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -		return max_cdclk_freq;
> -	else if (IS_CHERRYVIEW(dev_priv))
> -		return max_cdclk_freq*95/100;
> -	else if (HAS_DOUBLE_WIDE(display))
> -		return 2*max_cdclk_freq*90/100;
> -	else
> -		return max_cdclk_freq*90/100;
> +	return ppc * max_cdclk_freq * guardband / 100;
>  }
>  
>  /**

-- 
Jani Nikula, Intel