[PATCH v2 5/5] drm/i915/adlp+/dp_mst: Align master transcoder disabling with spec wrt. DP2 config

[Luca Coelho]

On Wed, 2024-10-30 at 21:23 +0200, Imre Deak wrote:
> On ADLP+ during modeset disabling, disable the DP2 configuration for MST
> master transcoders as required by the specification.
> 
> Bspec: 55424, 54128, 65448, 68849

Just curious how this change is related to so many bspecs...?


> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d82bc1bf8b68f..6adbc7d0b90d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3062,6 +3062,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>  
>  	intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
>  
> +	intel_ddi_config_transcoder_dp2(old_crtc_state, false);
> +
>  	/*
>  	 * From TGL spec: "If single stream or multi-stream master transcoder:
>  	 * Configure Transcoder Clock select to direct no clock to the

Regardless:

Reviewed-by: Luca Coelho <luciano.coelho at intel.com>

--
Cheers,
Luca.