[PATCH 1/2] drm/xe: Fix DSB buffer coherency

[Maarten Lankhorst]

Den 2024-09-13 kl. 14:04, skrev Matthew Auld:
> On 13/09/2024 12:47, Maarten Lankhorst wrote:
>> Add the scanout flag to force WC caching, and add the memory barrier
>> where needed.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
>> ---
>>   drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>> index f99d901a3214f..f7949bf5426af 100644
>> --- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>> +++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>> @@ -48,11 +48,12 @@ bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *d
>>       if (!vma)
>>           return false;
>>   +    /* Set scanout flag for WC mapping */
>>       obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe),
>>                      NULL, PAGE_ALIGN(size),
>>                      ttm_bo_type_kernel,
>>                      XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
>> -                   XE_BO_FLAG_GGTT);
>> +                   XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT);
>>       if (IS_ERR(obj)) {
>>           kfree(vma);
>>           return false;
>> @@ -73,5 +74,5 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
>>     void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
>>   {
>> -    /* TODO: add xe specific flush_map() for dsb buffer object. */
>> +    xe_device_wmb(dsb_buf->vma->bo->tile->xe);
> 
> Kind of orthogonal, but we could maybe also move the l2 flush here? I assume it's better to flush once at the end.
Eww, I didn't see that one. I totally would have if I saw it, the amount of calls for a single 4 byte write would remove any point of using DSB on BMG otherwise.

I'll send a followup patch. :)
> Reviewed-by: Matthew Auld <matthew.auld at intel.com>
> 
>>   }