[PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit
Ankit Nautiyal
ankit.k.nautiyal at intel.com
Tue Sep 17 17:41:56 UTC 2024
For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.
This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266
Rev2:
-Drop new member link_n_extended.
-Avoid WA framework for XE
Ankit Nautiyal (4):
Add bits for link_n_exended for DISPLAY >= 14
drm/i915/display: Limit m/n ratio to 10 for display > 12
drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
ratio > 10
drivers/gpu/drm/i915/display/intel_display.c | 147 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.h | 15 +-
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 62 ++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 5 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 37 +++--
drivers/gpu/drm/i915/display/intel_fdi.c | 15 +-
.../gpu/drm/i915/display/intel_pch_display.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 7 +
9 files changed, 243 insertions(+), 51 deletions(-)
--
2.45.2
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