[PATCH 3/3] drm/i915/dp: Extract intel_edp_set_sink_rates()

[Jani Nikula]

On Wed, 18 Sep 2024, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Declutter intel_edp_init_dpcd() a bit by extracting the sink
> rates probing into its own function.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 76 +++++++++++++------------
>  1 file changed, 40 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6a1b0e93a1fc..ae3f242fa925 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4066,6 +4066,45 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
>  	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
>  }
>  
> +static void
> +intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> +{
> +	intel_dp->num_sink_rates = 0;
> +
> +	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> +		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> +		int i;
> +
> +		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
> +				 sink_rates, sizeof(sink_rates));
> +
> +		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
> +			int val = le16_to_cpu(sink_rates[i]);
> +
> +			if (val == 0)
> +				break;
> +
> +			/* Value read multiplied by 200kHz gives the per-lane
> +			 * link rate in kHz. The source rates are, however,
> +			 * stored in terms of LS_Clk kHz. The full conversion
> +			 * back to symbols is
> +			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
> +			 */
> +			intel_dp->sink_rates[i] = (val * 200) / 10;
> +		}
> +		intel_dp->num_sink_rates = i;
> +	}
> +
> +	/*
> +	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
> +	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
> +	 */
> +	if (intel_dp->num_sink_rates)
> +		intel_dp->use_rate_select = true;
> +	else
> +		intel_dp_set_sink_rates(intel_dp);

Isn't this kind of in the wrong place, it's not eDP?

> +}
> +
>  static bool
>  intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
> @@ -4110,42 +4149,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>  	 */
>  	intel_psr_init_dpcd(intel_dp);
>  
> -	/* Clear the default sink rates */
> -	intel_dp->num_sink_rates = 0;
> -
> -	/* Read the eDP 1.4+ supported link rates. */
> -	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> -		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> -		int i;
> -
> -		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
> -				sink_rates, sizeof(sink_rates));
> -
> -		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
> -			int val = le16_to_cpu(sink_rates[i]);
> -
> -			if (val == 0)
> -				break;
> -
> -			/* Value read multiplied by 200kHz gives the per-lane
> -			 * link rate in kHz. The source rates are, however,
> -			 * stored in terms of LS_Clk kHz. The full conversion
> -			 * back to symbols is
> -			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
> -			 */
> -			intel_dp->sink_rates[i] = (val * 200) / 10;
> -		}
> -		intel_dp->num_sink_rates = i;
> -	}
> -
> -	/*
> -	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
> -	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
> -	 */
> -	if (intel_dp->num_sink_rates)
> -		intel_dp->use_rate_select = true;
> -	else
> -		intel_dp_set_sink_rates(intel_dp);
> +	intel_edp_set_sink_rates(intel_dp);
>  	intel_dp_set_max_sink_lane_count(intel_dp);
>  
>  	/* Read the eDP DSC DPCD registers */

-- 
Jani Nikula, Intel