[PATCH 4/4] drm/i915: Switch over to gen3 irq code on gen2

[Ville Syrjälä]

On Fri, Sep 27, 2024 at 05:35:45PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The only real reason why we have the gen2 vs. gen3+ split
> in irq handling is that bspec claims that IIR/IMR/IER/ISR
> and EMR are only 16 bits on gen2, as opposed to being 32
> bits on gen3+. That doesn't seem to be a meaningful
> distinction as 32bit access to these registers works
> perfectly fine on gen2
> 
> Interestingly the 16 msbs of IMR are in fact hardcoded
> to 1 on gen2, which to me indicates that 32bit access
> was the plan all along, and perhaps someone just forgot
> to update the spec.
> 
> Nuke the special 16bit gen2 irq code and switch over to
> the gen3 code.
> 
> Gen2 doesn't have the ASLE interrupt, which just needs
> a small tweak in i915_irq_postinstall().
> 
> And so far we've not had a codepath that could enable the
> legacy BLC interrupt on gen2. Now we do, but we'll never
> actually do it since gen2 machines don't have OpRegion.
> (and neither do i915/i945 machines btw). On these older
> platforms the legacy BLC interrupt is meant to be used
> in conjunction with the LBPC backlight stuff, but we
> never actually switch off the legacy/combination mode
> and thus don't use the interrupt either.
> 
> This was quickly smoke tested on all gen2 variants.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Hmm. I guess I should do this to the gt code as well.
But I'll hold off on that for the moment.

-- 
Ville Syrjälä
Intel