[PATCH 1/4] drm/i915: Apply the combo PLL frac w/a on DG1

[Imre Deak]

On Tue, Apr 01, 2025 at 07:37:49PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> DG1 apparently needs the combo PLL fractional divider w/a
> with 38.4 MHz refclk as well. This isn't listed in bspec, but
> looking at the hsd it looks like it was possibly just missed
> due to no one having a DG1 around at the time.
> 
> This gives us slightly more accurate clocks on DG1.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ec7feef1ef59..76ab55ee4b80 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2604,6 +2604,7 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
>  {
>  	return ((display->platform.elkhartlake &&
>  		 IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
> +		 display->platform.dg1 ||
>  		 display->platform.tigerlake ||
>  		 display->platform.alderlake_s ||
>  		 display->platform.alderlake_p) &&
> -- 
> 2.45.3
>