[PATCH v2 2/4] drm/i915: Simplify combo PLL frac w/a

[Imre Deak]

On Wed, Apr 02, 2025 at 08:17:20PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> We are applying the combo PLL frac w/a to all TGL+ platforms, except
> RKL. I *think* all RKL machines use a 24 MHz refclk (certainly all
> machines in our CI do) and so technically never need the adjustment.
> But let's assume the hardware is exactly the same anyway and simplify
> the code by applying the w/a to all TGL+ platforms.
> 
> v2: Keep the 38.4 MHz check
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 76ab55ee4b80..84df41086a89 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2604,11 +2604,8 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
>  {
>  	return ((display->platform.elkhartlake &&
>  		 IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
> -		 display->platform.dg1 ||
> -		 display->platform.tigerlake ||
> -		 display->platform.alderlake_s ||
> -		 display->platform.alderlake_p) &&
> -		 display->dpll.ref_clks.nssc == 38400;
> +		DISPLAY_VER(display) >= 12) &&
> +		display->dpll.ref_clks.nssc == 38400;
>  }
>  
>  struct icl_combo_pll_params {
> -- 
> 2.45.3
>