[PATCH 2/3] drm/i915/dsi: Don't set/read the DSI C clock divider on GLK

[Jani Nikula]

On Fri, 14 Mar 2025, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> GLK doesn't use the DSI C clock at all, no need to program
> the divider for it. Bspec even says: "Do not program this field".
>
> However looks like some firmware versions program this and
> some do not. In order to avoid bogus fastset mismatches
> we should also filter it out during readout.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> index 2ed47e7d1051..0c88924bc2cd 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> @@ -356,6 +356,8 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
>  	u32 pclk;
>  
>  	config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);
> +	if (IS_GEMINILAKE(dev_priv))
> +		config->dsi_pll.ctrl &= ~BXT_DSIC_16X_BY2;

~BXT_DSIC_16X_MASK ?

Other than that,

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

Also needs a rebase on struct intel_display changes...


>  
>  	pclk = bxt_dsi_pclk(encoder, config);
>  
> @@ -514,7 +516,9 @@ int bxt_dsi_pll_compute(struct intel_encoder *encoder,
>  	 * Spec says both have to be programmed, even if one is not getting
>  	 * used. Configure MIPI_CLOCK_CTL dividers in modeset
>  	 */
> -	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
> +	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2;
> +	if (!IS_GEMINILAKE(dev_priv))
> +		config->dsi_pll.ctrl |= BXT_DSIC_16X_BY2;
>  
>  	/* As per recommendation from hardware team,
>  	 * Prog PVD ratio =1 if dsi ratio <= 50

-- 
Jani Nikula, Intel