[PATCH v2 1/5] drm/i915: use 32-bit access for gen2 irq registers

[Ville Syrjälä]

On Wed, Apr 09, 2025 at 05:23:43PM +0300, Jani Nikula wrote:
> We've previously switched from 16-bit to 32-bit access for gen2 irq
> registers, but one was left behind. Fix it.
> 
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index a6613eed3398..cf31e8fecd8d 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1782,8 +1782,6 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
>  		gt->ier = intel_uncore_read(uncore, VLV_IER);
>  	else if (HAS_PCH_SPLIT(i915))
>  		gt->ier = intel_uncore_read(uncore, DEIER);
> -	else if (GRAPHICS_VER(i915) == 2)
> -		gt->ier = intel_uncore_read16(uncore, GEN2_IER);
>  	else
>  		gt->ier = intel_uncore_read(uncore, GEN2_IER);
>  }
> -- 
> 2.39.5

-- 
Ville Syrjälä
Intel