[PATCH] drm/i915/dp: Clear TRAINING_PATTERN_SET (DPCD 00102h) before starting Link Training

[Khaled Almahallawy]

The Link Layer Source CTS test 4.3.1.14 [1] fails at the beginning
(before 1st Link Training) due to the following issue:

"Source DUT does not terminate Link Training by writing 00h to the
TRAINING_PATTERN_SET"

According to the DP 2.1 specs [2], [3], [4], the TRAINING_PATTERN_SET
register must be set to 00h before initiating the Link Training sequence.
This is also confrimed by the Link Layer CTS tests [1] and [5] in step 3 of
its procedure that clearing TRAINING_PATTERN_SET is a pass/fail criterion.

This patch fixes the issue by explicitly clearing the DPCD training pattern
(TRAINING_PATTERN_SET = 00h) before starting Link Training.

[1] DP2.1 Link Layer CTS - 4.3.1.14 Successful Link Training at All
Supported Lane Counts and UHBR Link Speeds
[2] DP2.1 Specs - Figure 3-12: Link Training LANEx_CR_DONE Sequence
[3] DP2.1 Specs - Figure 3-14: Link Training LANEx_CR_DONE Sequence
for Maximum Link Data Bandwidth Policy
[4] DP2.1 Specs - Figure 3-52: 128b/132b DP DPTX LANEx_CHANNEL_EQ_DONE
Sequence
[5] DP2.1 Link Layer CTS - 4.9.1.1 With 1 emulated LTTPR, Successful
Link Training at all Supported Lane Counts and Link Speeds

Cc: Imre Deak <imre.deak at intel.com>
Cc: Jani Nikula <jani.nikula at intel.com>
Signed-off-by: Charlton Lin <charlton.lin at intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c | 20 ++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a479b63112ea..9e402ad6467c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -766,6 +766,16 @@ static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
 				      crtc_state->enhanced_framing);
 }
 
+static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
+						   enum drm_dp_phy dp_phy)
+{
+	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
+	u8 val = DP_TRAINING_PATTERN_DISABLE;
+
+	return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
+}
+
+
 /*
  * Prepare link training by configuring the link parameters. On DDI platforms
  * also enable the port here.
@@ -813,6 +823,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
 	 * Spec DP2.1 Section 3.5.2.16
 	 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
 	 */
+	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
 	intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
 	intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
 				    rate_select);
@@ -1081,15 +1092,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 	return channel_eq;
 }
 
-static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
-						   enum drm_dp_phy dp_phy)
-{
-	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
-	u8 val = DP_TRAINING_PATTERN_DISABLE;
-
-	return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
-}
-
 static int
 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp,
 			    const struct intel_crtc_state *crtc_state)
-- 
2.43.0