[PATCH 08/15] drm/i915/psr: Store max PSR2/Panel Replay latency in crtc_state

[Ankit Nautiyal]

Add a new `psr_latency` field to intel_crtc_state to hold the maximum
link wake latency for PSR2 and Panel Replay. This value is computed during
intel_dp_compute_config() when encoder context is available.

This allows the latency to be used later during guardband calculations,
where only the CRTC state is available and encoder-specific functions
can't be accessed.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c            | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4d9df803ad47..91d19906f85e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1119,6 +1119,7 @@ struct intel_crtc_state {
 	bool enable_psr2_su_region_et;
 	bool req_psr2_sdp_prior_scanline;
 	bool has_panel_replay;
+	int psr_latency; /* PSR2/PR Vblank time */
 	bool wm_level_disabled;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a7ecc8ad67f2..59808acbc314 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3299,6 +3299,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	intel_dp_compute_as_sdp(intel_dp, pipe_config);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
 	intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
+
+	pipe_config->psr_latency =
+		intel_psr_compute_max_link_wake_latency(intel_dp, pipe_config, false);
+
 	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
-- 
2.45.2