[PATCH 06/19] drm/i915/tc: Use the cached max lane count value

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Tuesday, 5 August 2025 10.37
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Subject: [PATCH 06/19] drm/i915/tc: Use the cached max lane count value
> 
> Use the PHY's cached max lane count value on all platforms similarly to
> LNL+. On LNL+ using the cached value is mandatory - since the
> corresponding HW register field can get cleared by the time the value is queried - on earlier platforms there isn't a problem with
> using the HW register instead. Having a uniform way to query the value still makes sense and it's also a bit more efficient, so do
> that.
> 
> Signed-off-by: Imre Deak <imre.deak at intel.com>

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index dec54cb0c8c63..d89c174bcb836 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -395,15 +395,11 @@ static void read_pin_configuration(struct intel_tc_port *tc)
> 
>  int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)  {
> -	struct intel_display *display = to_intel_display(dig_port);
>  	struct intel_tc_port *tc = to_tc_port(dig_port);
> 
>  	if (!intel_encoder_is_tc(&dig_port->base))
>  		return 4;
> 
> -	if (DISPLAY_VER(display) < 20)
> -		return get_max_lane_count(tc);
> -
>  	return tc->max_lane_count;
>  }
> 
> --
> 2.49.1