✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Allow display PHYs to reset power state (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Allow display PHYs to reset power state (rev2)
URL   : https://patchwork.freedesktop.org/series/144102/
State : warning

== Summary ==

Error: dim checkpatch failed
bf57b86fbb00 drm/i915/display: Drop crtc_state from C10/C20 pll programming
-:57: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2053:
+					      const struct intel_c10pll_state * const *tables, int port_clock, bool is_dp,

-:98: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2083:
+						 crtc_state->port_clock, intel_crtc_has_dp_encoder(crtc_state),

-:252: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#252: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3092:
+			      intel_crtc_has_dp_encoder(crtc_state), crtc_state->port_clock, crtc_state->lane_count);

-:254: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3094:
+
+}

total: 0 errors, 3 warnings, 1 checks, 225 lines checked
b698d92d4b09 drm/i915/display: Allow display PHYs to reset power state
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#12: 
1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.

-:41: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#41: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3572:
+}
+/*

-:71: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#71: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3602:
+		intel_c10pll_calc_state_from_table(encoder, mtl_c10_edp_tables, port_clock, true, &pll_state);

total: 0 errors, 2 warnings, 1 checks, 82 lines checked