[PATCH 07/12] drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Convert the CHV EU/slice fuse bits to the modern REG_BIT()/etc.
style.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 26 +++++++++++--------------
 drivers/gpu/drm/i915/gt/intel_sseu.c    | 12 ++++--------
 2 files changed, 15 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c58192e6f078..f5ac73a2ed7d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -934,12 +934,12 @@
 #define CHV_POWER_SS0_SIG1			_MMIO(0xa720)
 #define CHV_POWER_SS0_SIG2			_MMIO(0xa724)
 #define CHV_POWER_SS1_SIG1			_MMIO(0xa728)
-#define   CHV_SS_PG_ENABLE			(1 << 1)
-#define   CHV_EU08_PG_ENABLE			(1 << 9)
-#define   CHV_EU19_PG_ENABLE			(1 << 17)
-#define   CHV_EU210_PG_ENABLE			(1 << 25)
+#define   CHV_SS_PG_ENABLE			REG_BIT(1)
+#define   CHV_EU08_PG_ENABLE			REG_BIT(9)
+#define   CHV_EU19_PG_ENABLE			REG_BIT(17)
+#define   CHV_EU210_PG_ENABLE			REG_BIT(25)
 #define CHV_POWER_SS1_SIG2			_MMIO(0xa72c)
-#define   CHV_EU311_PG_ENABLE			(1 << 1)
+#define   CHV_EU311_PG_ENABLE			REG_BIT(1)
 
 #define GEN7_SARCHKMD				_MMIO(0xb000)
 #define   GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)
@@ -1437,16 +1437,12 @@
 #define   XEHP_CCS_MODE_CSLICE(cslice, ccs)	(ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH))
 
 #define CHV_FUSE_GT				_MMIO(VLV_GUNIT_BASE + 0x2168)
-#define   CHV_FGT_DISABLE_SS0			(1 << 10)
-#define   CHV_FGT_DISABLE_SS1			(1 << 11)
-#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT		16
-#define   CHV_FGT_EU_DIS_SS0_R0_MASK		(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
-#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT		20
-#define   CHV_FGT_EU_DIS_SS0_R1_MASK		(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
-#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT		24
-#define   CHV_FGT_EU_DIS_SS1_R0_MASK		(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
-#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT		28
-#define   CHV_FGT_EU_DIS_SS1_R1_MASK		(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
+#define   CHV_FGT_DISABLE_SS0			REG_BIT(10)
+#define   CHV_FGT_DISABLE_SS1			REG_BIT(11)
+#define   CHV_FGT_EU_DIS_SS0_R0_MASK		REG_GENMASK(19, 16)
+#define   CHV_FGT_EU_DIS_SS0_R1_MASK		REG_GENMASK(23, 20)
+#define   CHV_FGT_EU_DIS_SS1_R0_MASK		REG_GENMASK(27, 24)
+#define   CHV_FGT_EU_DIS_SS1_R1_MASK		REG_GENMASK(31, 28)
 
 #define BCS_SWCTRL				_MMIO(0x22200)
 #define   BCS_SRC_Y				REG_BIT(0)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index e4538dd726c8..8ae1208f9da5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -335,10 +335,8 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
 
 	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 		u8 disabled_mask =
-			((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
-			 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
-			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
-			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
+			REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) |
+			REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK);
 
 		sseu->subslice_mask.hsw[0] |= BIT(0);
 		sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
@@ -346,10 +344,8 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
 
 	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 		u8 disabled_mask =
-			((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
-			 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
-			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
-			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
+			REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) |
+			REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK);
 
 		sseu->subslice_mask.hsw[0] |= BIT(1);
 		sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
-- 
2.45.3