[PATCH 4/8] drm/i915: Hook in display GTT faults for IVB/HSW

[Govindapillai, Vinod]

On Thu, 2025-01-16 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Dump out the display fault information from the IVB/HSW
> error interrupt handler.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_irq.c  | 47 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               | 11 +++++
>  2 files changed, 58 insertions(+)

Bspec 8203 reference might be helpful I guess.

Reviewed-by: Vinod Govindapillai <vinod.govindapillai at intel.com>


> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 1b3b6b8bc794..70e5326b86d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -669,15 +669,57 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>  		intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
>  }
>  
> +static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe)
> +{
> +	switch (pipe) {
> +	case PIPE_A:
> +		return ERR_INT_SPRITE_A_FAULT |
> +			ERR_INT_PRIMARY_A_FAULT |
> +			ERR_INT_CURSOR_A_FAULT;
> +	case PIPE_B:
> +		return ERR_INT_SPRITE_B_FAULT |
> +			ERR_INT_PRIMARY_B_FAULT |
> +			ERR_INT_CURSOR_B_FAULT;
> +	case PIPE_C:
> +		return ERR_INT_SPRITE_C_FAULT |
> +			ERR_INT_PRIMARY_C_FAULT |
> +			ERR_INT_CURSOR_C_FAULT;
> +	default:
> +		return 0;
> +	}
> +}
> +
> +static const struct pipe_fault_handler ivb_pipe_fault_handlers[] = {
> +	{ .fault = ERR_INT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_SPRITE0, },
> +	{ .fault = ERR_INT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_PRIMARY, },
> +	{ .fault = ERR_INT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_CURSOR, },
> +	{ .fault = ERR_INT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_SPRITE0, },
> +	{ .fault = ERR_INT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_PRIMARY, },
> +	{ .fault = ERR_INT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_CURSOR, },
> +	{ .fault = ERR_INT_SPRITE_C_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_SPRITE0, },
> +	{ .fault = ERR_INT_PRIMARY_C_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_PRIMARY, },
> +	{ .fault = ERR_INT_CURSOR_C_FAULT, .handle = handle_plane_fault, .plane_id =
> PLANE_CURSOR, },
> +	{}
> +};
> +
>  static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
>  {
> +	struct intel_display *display = &dev_priv->display;
>  	u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);
>  	enum pipe pipe;
>  
>  	if (err_int & ERR_INT_POISON)
>  		drm_err(&dev_priv->drm, "Poison interrupt\n");
>  
> +	if (err_int & ERR_INT_INVALID_GTT_PTE)
> +		drm_err_ratelimited(display->drm, "Invalid GTT PTE\n");
> +
> +	if (err_int & ERR_INT_INVALID_PTE_DATA)
> +		drm_err_ratelimited(display->drm, "Invalid PTE data\n");
> +
>  	for_each_pipe(dev_priv, pipe) {
> +		u32 fault_errors;
> +
>  		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
>  			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
>  
> @@ -687,6 +729,11 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
>  			else
>  				hsw_pipe_crc_irq_handler(dev_priv, pipe);
>  		}
> +
> +		fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe);
> +		if (fault_errors)
> +			intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers,
> +						     pipe, fault_errors);
>  	}
>  
>  	intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 765e6c0528fb..9021f3ead7e6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -374,6 +374,17 @@
>  
>  #define GEN7_ERR_INT	_MMIO(0x44040)
>  #define   ERR_INT_POISON		(1 << 31)
> +#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
> +#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
> +#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
> +#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
> +#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
> +#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
> +#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
> +#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
> +#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
> +#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
> +#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
>  #define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
>  #define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
>  #define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)