✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Allow display PHYs to reset power state (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Allow display PHYs to reset power state (rev3)
URL   : https://patchwork.freedesktop.org/series/144102/
State : warning

== Summary ==

Error: dim checkpatch failed
81afe0ccad86 drm/i915/display: Drop crtc_state from C10/C20 pll programming
-:60: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#60: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2052:
+					      const struct intel_c10pll_state * const *tables, int port_clock, bool is_dp,

-:256: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3093:
+			      intel_crtc_has_dp_encoder(crtc_state), crtc_state->port_clock, crtc_state->lane_count);

-:258: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#258: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3095:
+
+}

total: 0 errors, 2 warnings, 1 checks, 226 lines checked
e2cb013f4ec8 drm/i915/display: Allow display PHYs to reset power state
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#12: 
1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.

-:38: ERROR:CODE_INDENT: code indent should use tabs where possible
#38: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3566:
+        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);$

-:38: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#38: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3566:
+        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);$

total: 1 errors, 2 warnings, 0 checks, 89 lines checked