[PATCH 02/12] drm/i915: Relocate RING_FAULT bits

[Andi Shyti]

Hi Ville,

On Wed, Feb 12, 2025 at 01:19:30AM +0200, Ville Syrjala wrote:
> We share the bit definitions between the older
> RING_FAULT registers and their various gen12+
> counterparts. Currently the bits are defined next
> to the new registers which isn't what we typically do.
> 
> Move the bit definitions next the older register offsets,
> and leave breadcrumbs around the gen12+ registers to make
> it easier to find the right bits.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 5e4f0545f558..2d3da98e94f0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -326,6 +326,11 @@
>  							    _RING_FAULT_REG_VCS, \
>  							    _RING_FAULT_REG_VECS, \
>  							    _RING_FAULT_REG_BCS))
> +#define   GEN8_RING_FAULT_ENGINE_ID(x)		(((x) >> 12) & 0x1f)
> +#define   RING_FAULT_GTTSEL_MASK		(1 << 11)
> +#define   RING_FAULT_SRCID(x)			(((x) >> 3) & 0xff)
> +#define   RING_FAULT_FAULT_TYPE(x)		(((x) >> 1) & 0x3)
> +#define   RING_FAULT_VALID			(1 << 0)

Perhaps we can add a comment here to tell that this is referenced
below. But not a big deal, though.

Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com>

Thanks,
Andi

>  
>  #define ERROR_GEN6				_MMIO(0x40a0)