[PATCH 10/12] drm/i915: Reoder BDW+ EU/slice fuse bits

[Andi Shyti]

Hi Ville
On Wed, Feb 12, 2025 at 01:19:38AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> We customarily define the bits of a register in big endian
> order. Reorder the BDW+ fuse bits to match.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com>

Thanks,
Andi