[PATCH 12/20] drm/i915/display: Extend WA 14015406119 for PSR2

[Nautiyal, Ankit K]

On 2/26/2025 7:25 PM, Ville Syrjälä wrote:
> On Mon, Feb 24, 2025 at 11:47:09AM +0530, Ankit Nautiyal wrote:
>> Wa_14015406119 is required for PSR1/2 while working with fixed refresh
>> rate with VRR timing generator.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 0db84af1063a..752ed44d8892 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2508,8 +2508,9 @@ static bool intel_crtc_needs_wa_14015401596(const struct intel_crtc_state *crtc_
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>>   
>> -	return intel_vrr_possible(crtc_state) && crtc_state->has_psr &&
>> -		IS_DISPLAY_VER(display, 13, 14);
>> +	return intel_vrr_possible(crtc_state) &&
>> +	       (crtc_state->has_psr || crtc_state->has_sel_update) &&
> I presume you wanted some kind of use_vrr_tg_always() check here instead
> of that has_sel_update thing (which is a nop since it should never be
> set unless has_psr is also set)?
Thanks for pointing this out.
I think I misunderstood the flags. Its clearly documented that `has_psr` 
is always set for psr1/2, panel replay.

Also we already have check for vrr_possible which checks flipline, so 
this is covered for our case.

I'll drop this patch.

Regards,

Ankit

>
>> +	       IS_DISPLAY_VER(display, 13, 14);
>>   }
>>   
>>   static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
>> -- 
>> 2.45.2