[PATCH 1/2] drm/i915/display_wa: Add helpers to check wa

Lucas De Marchi lucas.demarchi at intel.com
Wed Jul 2 20:25:21 UTC 2025


On Wed, Jul 02, 2025 at 10:40:34PM +0300, Ville Syrjälä wrote:
>On Wed, Jul 02, 2025 at 02:16:18PM +0530, Ankit Nautiyal wrote:
>> Introduce a generic helper to check display workarounds using an enum.
>>
>> Convert Wa_16023588340 to use the new interface, simplifying WA checks
>> and making future additions easier.
>>
>> v2: Use drm_WARN instead of MISSING_CASE and simplify intel_display_wa
>> macro. (Jani)
>>
>> Suggested-by: Jani Nikula <jani.nikula at intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_wa.c | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_display_wa.h |  9 +++++++++
>>  drivers/gpu/drm/i915/display/intel_fbc.c        |  2 +-
>>  3 files changed, 25 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
>> index f57280e9d041..f5e8d58d9a68 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
>> @@ -3,6 +3,8 @@
>>   * Copyright © 2023 Intel Corporation
>>   */
>>
>> +#include "drm/drm_print.h"
>> +
>>  #include "i915_reg.h"
>>  #include "intel_de.h"
>>  #include "intel_display_core.h"
>> @@ -39,3 +41,16 @@ void intel_display_wa_apply(struct intel_display *display)
>>  	else if (DISPLAY_VER(display) == 11)
>>  		gen11_display_wa_apply(display);
>>  }
>> +
>> +bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa)
>> +{
>> +	switch (wa) {
>> +	case INTEL_DISPLAY_WA_16023588340:
>> +		return intel_display_needs_wa_16023588340(display);
>> +	default:
>> +		drm_WARN(display->drm, 1, "Missing Wa number: %d\n", wa);
>> +		break;
>> +	}
>> +
>> +	return false;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
>> index babd9d16603d..146ee70d66f7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
>> @@ -21,4 +21,13 @@ static inline bool intel_display_needs_wa_16023588340(struct intel_display *disp
>>  bool intel_display_needs_wa_16023588340(struct intel_display *display);
>>  #endif
>>
>> +enum intel_display_wa {
>> +	INTEL_DISPLAY_WA_16023588340,
>
>How is anyone supposed to keep track of these random numbers
>and what they mean?

they mean there's a h/w workaround that requires that and this is the id
if you need to find more details about it or what platforms/IPs use
that.

>
>The only time I want to see these numbers is if I really have to
>open the spec/hsd for it to double check some details. Othwerwise
>it just seems like pointless noise that makes it harder to follow
>the code/figure out what the heck is going on.

what is the alternative? The current status quo checking by platform
and/or IP version, dissociated from the WA numbers?

Lucas De Marchi

>
>> +};
>> +
>> +bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa);
>> +
>> +#define intel_display_wa(__display, __wa) \
>> +	__intel_display_wa((__display), INTEL_DISPLAY_WA_##__wa)
>> +
>>  #endif
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index 6e26cb4c5724..e2e03af520b2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -1464,7 +1464,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
>>  		return 0;
>>  	}
>>
>> -	if (intel_display_needs_wa_16023588340(display)) {
>> +	if (intel_display_wa(display, 16023588340)) {
>>  		plane_state->no_fbc_reason = "Wa_16023588340";
>
>This here for instance is completely useless. I have no idea what that
>w/a is about or why it requires FBC to be disabled. And if I jump into
>intel_display_needs_wa_16023588340() I am none the wiser.
>
>>  		return 0;
>>  	}
>> --
>> 2.45.2
>
>-- 
>Ville Syrjälä
>Intel


More information about the Intel-gfx mailing list