[PATCH v2 4/4] drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

[Hogander, Jouni]

On Tue, 2025-07-22 at 09:07 -0300, Gustavo Sousa wrote:
> Quoting Jouni Högander (2025-07-22 07:13:17-03:00)
> > According to C10 VDR Register programming sequence we need set
> > C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers
> > from
> > MsgBus.
> > 
> > Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure
> > LFPS sending")
> > Suggested-by: Gustavo Sousa <gustavo.sousa at intel.com>
> > Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index a203937d66db..886eff874cb7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3258,6 +3258,11 @@ void intel_lnl_mac_transmit_lfps(struct
> > intel_encoder *encoder,
> >                 if (!(owned_lane_mask & lane_mask))
> >                         continue;
> > 
> > +                if (intel_encoder_is_c10phy(encoder))
> > +                        intel_cx0_rmw(encoder, lane_mask,
> > PHY_C10_VDR_CONTROL(1),
> > +                                      0,
> > C10_VDR_CTRL_MSGBUS_ACCESS,
> > +                                      MB_WRITE_COMMITTED);
> 
> This could be moved to be done just once, before the loop, replacing
> lane_mask with owned_lane_mask, no?

Yes, you are right on this. I will make the change and resend. I will
also add the Bspec reference.

BR,

Jouni Högander

> 
> --
> Gustavo Sousa
> 
> > +
> >                 intel_cx0_rmw(encoder, lane_mask,
> > PHY_CMN1_CONTROL(tx, 0),
> >                               CONTROL0_MAC_TRANSMIT_LFPS,
> >                               CONTROL0_MAC_TRANSMIT_LFPS,
> > MB_WRITE_COMMITTED);
> > -- 
> > 2.43.0
> >