[PATCH 04/28] drm/i915/writeback: Add writeback registers
Murthy, Arun R
arun.r.murthy at intel.com
Mon Jul 28 06:31:16 UTC 2025
On 25-07-2025 10:33, Suraj Kandpal wrote:
> Add writeback registers to its own file.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
> ---
> .../drm/i915/display/intel_writeback_reg.h | 136 ++++++++++++++++++
> 1 file changed, 136 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_writeback_reg.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_writeback_reg.h b/drivers/gpu/drm/i915/display/intel_writeback_reg.h
> new file mode 100644
> index 000000000000..ffe302ef3dd9
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_writeback_reg.h
> @@ -0,0 +1,136 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
After updating the copyright!
Reviewed-by: Arun R Murthy <arun.r.murthy at intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> +
> +#ifndef __INTEL_WRITEBACK_REGS_H__
> +#define __INTEL_WRITEBACK_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/* WD 0 and 1 */
> +#define TRANSCODER_WD0_OFFSET 0x6e000
> +#define TRANSCODER_WD1_OFFSET 0x6d800
> +
> +/* WD 0 and 1 */
> +#define PIPE_WD0_OFFSET 0x7e008
> +#define PIPE_WD1_OFFSET 0x7d008
> +
> +/* Gen12 WD */
> +#define _MMIO_WD(tc, wd0, wd1) _MMIO_TRANS((tc) - TRANSCODER_WD_0, wd0, wd1)
> +
> +#define WD_TRANS_ENABLE REG_BIT(31)
> +#define WD_TRANS_STATE REG_BIT(30)
> +
> +/* WD transcoder control */
> +#define _WD_TRANS_FUNC_CTL_0 0x6e400
> +#define _WD_TRANS_FUNC_CTL_1 0x6ec00
> +#define WD_TRANS_FUNC_CTL(tc) _MMIO_WD(tc,\
> + _WD_TRANS_FUNC_CTL_0,\
> + _WD_TRANS_FUNC_CTL_1)
> +
> +#define TRANS_WD_FUNC_ENABLE REG_BIT(31)
> +#define WD_TRIGGERED_CAP_MODE_ENABLE REG_BIT(30)
> +#define START_TRIGGER_FRAME REG_BIT(29)
> +#define STOP_TRIGGER_FRAME REG_BIT(28)
> +#define WD_INPUT_SELECT_MASK REG_GENMASK(14, 12)
> +#define WD_INPUT_PIPE_A REG_FIELD_PREP(WD_INPUT_SELECT_MASK, 0)
> +#define WD_INPUT_PIPE_B REG_FIELD_PREP(WD_INPUT_SELECT_MASK, 5)
> +#define WD_INPUT_PIPE_C REG_FIELD_PREP(WD_INPUT_SELECT_MASK, 6)
> +#define WD_INPUT_PIPE_D REG_FIELD_PREP(WD_INPUT_SELECT_MASK, 7)
> +#define WD_COLOR_MODE_MASK REG_GENMASK(22, 20)
> +#define WD_CONTROL_POINTERS REG_GENMASK(19, 18)
> +#define WD_DISABLE_POINTERS REG_FIELD_PREP(WD_CONTROL_POINTERS, 3)
> +#define WD_PIX_FMT_YUYV REG_FIELD_PREP(WD_COLOR_MODE_MASK, 1)
> +#define WD_PIX_FMT_XYUV8888 REG_FIELD_PREP(WD_COLOR_MODE_MASK, 2)
> +#define WD_PIX_FMT_XBGR8888 REG_FIELD_PREP(WD_COLOR_MODE_MASK, 3)
> +#define WD_PIX_FMT_Y410 REG_FIELD_PREP(WD_COLOR_MODE_MASK, 4)
> +#define WD_PIX_FMT_YUV422 REG_FIELD_PREP(WD_COLOR_MODE_MASK, 5)
> +#define WD_PIX_FMT_XBGR2101010 REG_FIELD_PREP(WD_COLOR_MODE_MASK, 6)
> +#define WD_PIX_FMT_RGB565 REG_FIELD_PREP(WD_COLOR_MODE_MASK, 7)
> +#define WD_FRAME_NUMBER_MASK REG_GENMASK(3, 0)
> +#define WD_FRAME_NUMBER(n) REG_FIELD_PREP(WD_FRAME_NUMBER_MASK, n)
> +
> +#define _WD_STRIDE_0 0x6e510
> +#define _WD_STRIDE_1 0x6ed10
> +#define WD_STRIDE(tc) _MMIO_WD(tc,\
> + _WD_STRIDE_0,\
> + _WD_STRIDE_1)
> +#define WD_STRIDE_MASK REG_GENMASK(15, 6)
> +
> +#define _WD_STREAMCAP_CTL0 0x6e590
> +#define _WD_STREAMCAP_CTL1 0x6ed90
> +#define WD_STREAMCAP_CTL(tc) _MMIO_WD(tc,\
> + _WD_STREAMCAP_CTL0,\
> + _WD_STREAMCAP_CTL1)
> +
> +#define WD_STREAM_CAP_MODE_EN REG_BIT(31)
> +#define WD_SLICING_STRAT_MASK REG_GENMASK(25, 24)
> +#define WD_SLICING_STRAT_1_1 REG_FIELD_PREP(WD_SLICING_STRAT_MASK, 0)
> +#define WD_SLICING_STRAT_2_1 REG_FIELD_PREP(WD_SLICING_STRAT_MASK, 1)
> +#define WD_SLICING_STRAT_4_1 REG_FIELD_PREP(WD_SLICING_STRAT_MASK, 2)
> +#define WD_SLICING_STRAT_8_1 REG_FIELD_PREP(WD_SLICING_STRAT_MASK, 3)
> +#define WD_STREAM_OVERRUN_STATUS 1
> +
> +#define _WD_SURF_0 0x6e514
> +#define _WD_SURF_1 0x6ed14
> +#define WD_SURF(tc) _MMIO_WD(tc,\
> + _WD_SURF_0,\
> + _WD_SURF_1)
> +
> +#define _WD_IMR_0 0x6e560
> +#define _WD_IMR_1 0x6ed60
> +#define WD_IMR(tc) _MMIO_WD(tc,\
> + _WD_IMR_0,\
> + _WD_IMR_1)
> +#define WD_FRAME_COMPLETE_INT REG_BIT(7)
> +#define WD_GTT_FAULT_INT REG_BIT(6)
> +#define WD_VBLANK_INT REG_BIT(5)
> +#define WD_OVERRUN_INT REG_BIT(4)
> +#define WD_CAPTURING_INT REG_BIT(3)
> +#define WD_WRITE_COMPLETE_INT REG_BIT(2)
> +
> +#define _WD_IIR_0 0x6e564
> +#define _WD_IIR_1 0x6ed64
> +#define WD_IIR(tc) _MMIO_WD(tc,\
> + _WD_IIR_0,\
> + _WD_IIR_1)
> +
> +#define _WD_FRAME_STATUS_0 0x6e568
> +#define _WD_FRAME_STATUS_1 0x6ed68
> +#define WD_FRAME_STATUS(tc) _MMIO_WD(tc,\
> + _WD_FRAME_STATUS_0,\
> + _WD_FRAME_STATUS_1)
> +
> +#define WD_FRAME_COMPLETE REG_BIT(31)
> +#define WD_STATE_MASK REG_GENMASK(26, 24)
> +#define WD_STATE_IDLE REG_FIELD_PREP(WD_STATE_MASK, 0)
> +#define WD_STATE_CAPSTART REG_FIELD_PREP(WD_STATE_MASK, 1)
> +#define WD_STATE_FRAME_START REG_FIELD_PREP(WD_STATE_MASK, 2)
> +#define WD_STATE_CAPACITIVE REG_FIELD_PREP(WD_STATE_MASK, 3)
> +#define WD_STATE_TG_DONE REG_FIELD_PREP(WD_STATE_MASK, 4)
> +#define WD_STATE_WDX_DONE REG_FIELD_PREP(WD_STATE_MASK, 5)
> +#define WD_STATE_QUICK_CAP REG_FIELD_PREP(WD_STATE_MASK, 6)
> +
> +#define _WD_27_M_0 0x6e524
> +#define _WD_27_M_1 0x6ed24
> +#define WD_27_M(tc) _MMIO_WD(tc,\
> + _WD_27_M_0,\
> + _WD_27_M_1)
> +
> +#define _WD_27_N_0 0x6e528
> +
> +/* Address looks wrong in bspec: */
> +#define _WD_27_N_1 0x6ec28
> +#define WD_27_N(tc) _MMIO_WD(tc,\
> + _WD_27_N_0,\
> + _WD_27_N_1)
> +
> +#define _WD_TAIL_CFG_0 0x6e520
> +#define _WD_TAIL_CFG_1 0x6ed20
> +
> +#define WD_TAIL_CFG(tc) _MMIO_WD(tc,\
> + _WD_TAIL_CFG_0,\
> + _WD_TAIL_CFG_1)
> +
> +#endif /* __INTEL_WRITEBACK_REGS_H__ */
More information about the Intel-gfx
mailing list