[PATCH 1/7] drm/i915: Drop PIPEDMC faults from the fault mask on LNL+

[Ville Syrjälä]

On Tue, May 13, 2025 at 12:47:59PM +0300, Luca Coelho wrote:
> On Mon, 2025-05-12 at 13:33 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > On LNL+ PIPEDMC faults are reported via PIPEDMC interrupts
> > instead of the direct DE_PIPE_* reporting used on earlier
> > platforms. Drop the relevant bits from the fault mask.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_irq.c | 10 +++++++++-
> >  drivers/gpu/drm/i915/i915_reg.h                  |  4 ++--
> >  2 files changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> > index 3e73832e5e81..a7130b14aace 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> > @@ -1016,7 +1016,15 @@ static u32 gen8_de_port_aux_mask(struct intel_display *display)
> >  
> >  static u32 gen8_de_pipe_fault_mask(struct intel_display *display)
> >  {
> > -	if (DISPLAY_VER(display) >= 14)
> > +	if (DISPLAY_VER(display) >= 20)
> > +		return MTL_PLANE_ATS_FAULT |
> > +			GEN9_PIPE_CURSOR_FAULT |
> > +			GEN11_PIPE_PLANE5_FAULT |
> > +			GEN9_PIPE_PLANE4_FAULT |
> > +			GEN9_PIPE_PLANE3_FAULT |
> > +			GEN9_PIPE_PLANE2_FAULT |
> > +			GEN9_PIPE_PLANE1_FAULT;
> > +	else if (DISPLAY_VER(display) >= 14)
> >  		return MTL_PIPEDMC_ATS_FAULT |
> >  			MTL_PLANE_ATS_FAULT |
> >  			GEN12_PIPEDMC_FAULT |
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 2e4190da3e0d..2d0e04eae763 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2126,8 +2126,8 @@
> >  #define  GEN8_PIPE_CDCLK_CRC_ERROR	REG_BIT(29)
> >  #define  GEN8_PIPE_CDCLK_CRC_DONE	REG_BIT(28)
> >  #define  GEN12_PIPEDMC_INTERRUPT	REG_BIT(26) /* tgl+ */
> > -#define  GEN12_PIPEDMC_FAULT		REG_BIT(25) /* tgl+ */
> > -#define  MTL_PIPEDMC_ATS_FAULT		REG_BIT(24) /* mtl+ */
> > +#define  GEN12_PIPEDMC_FAULT		REG_BIT(25) /* tgl-mtl */
> > +#define  MTL_PIPEDMC_ATS_FAULT		REG_BIT(24) /* mtl */
> >  #define  GEN11_PIPE_PLANE7_FAULT	REG_BIT(22) /* icl/tgl */
> >  #define  GEN11_PIPE_PLANE6_FAULT	REG_BIT(21) /* icl/tgl */
> >  #define  GEN11_PIPE_PLANE5_FAULT	REG_BIT(20) /* icl+ */
> 
> Out of curiosity, what happens without this patch? Is there going to be
> possible garbage in those bits?

They seem to be unused and tied to zero. So no garbage.

> If so, isn't that an actual bug in the
> current LNL implementation and unrelated to your flip queue preparation
> work?

I noticed the issue when I was hooking up the PIPEDMC interrupts.

> 
> Reviewed-by: Luca Coelho <luciano.coelho at intel.com>
> 
> --
> Cheers,
> Luca.

-- 
Ville Syrjälä
Intel