[PATCH v2] drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP

[Hogander, Jouni]

On Mon, 2025-05-05 at 09:09 +0530, Ankit Nautiyal wrote:
> The register EMP_AS_SDP_TL (MTL) was introduced for configuring the
> double buffering point and transmission line for all
> HDMI2.1 Extended Metadata Packets (VT-EMP for VRR, CVT-EMP for DSC
> etc).
> This was also intended to be configured for DP to HDMI2.1 PCON to
> support VRR.
> 
> From BMG and LNL+ onwards, this register was extended to Display Port
> Adaptive Sync SDP to have a common register to configure double
> buffering point and transmission line for both HDMI EMPs and DP VRR
> related
> packets.
> 
> Currently, we do not support VRR for either native HDMI or via PCON.
> However we need to configure this for DP SDP case. As per the spec,
> program the register to set Vsync start as the double buffering point
> for DP AS SDP.
> 
> v2:
> -Make the helper more readable. (Jani)
> -Add more information in commit message and comment.
> 
> Bspec:70984, 71197
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> Tested-by: Jouni Högander <jouni.hogander at intel.com>

Reviewed-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 23
> +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr_regs.h |  6 +++++
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index c6565baf815a..c55b8144e234 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -576,6 +576,25 @@ bool intel_vrr_always_use_vrr_tg(struct
> intel_display *display)
>  	return false;
>  }
>  
> +static
> +void intel_vrr_set_db_point_and_transmission_line(const struct
> intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	/*
> +	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for
> programming
> +	 * double buffering point and transmission line for VRR
> packets for
> +	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> +	 * Since currently we support VRR only for DP/eDP, so this
> is programmed
> +	 * to for Adaptive Sync SDP to Vsync start.
> +	 */
> +	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display)
> >= 20)
> +		intel_de_write(display,
> +			       EMP_AS_SDP_TL(display,
> cpu_transcoder),
> +			       EMP_AS_SDP_DB_TL(crtc_state-
> >vrr.vsync_start));
> +}
> +
>  void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display =
> to_intel_display(crtc_state);
> @@ -595,6 +614,8 @@ void intel_vrr_enable(const struct
> intel_crtc_state *crtc_state)
>  		       TRANS_PUSH_EN);
>  
>  	if (!intel_vrr_always_use_vrr_tg(display)) {
> +		intel_vrr_set_db_point_and_transmission_line(crtc_st
> ate);
> +
>  		if (crtc_state->cmrr.enable) {
>  			intel_de_write(display,
> TRANS_VRR_CTL(display, cpu_transcoder),
>  				       VRR_CTL_VRR_ENABLE |
> VRR_CTL_CMRR_ENABLE |
> @@ -646,6 +667,8 @@ void intel_vrr_transcoder_enable(const struct
> intel_crtc_state *crtc_state)
>  	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
>  		       TRANS_PUSH_EN);
>  
> +	intel_vrr_set_db_point_and_transmission_line(crtc_state);
> +
>  	intel_de_write(display, TRANS_VRR_CTL(display,
> cpu_transcoder),
>  		       VRR_CTL_VRR_ENABLE |
> trans_vrr_ctl(crtc_state));
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 6ed0e0dc97e7..09cdd50d6187 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -108,6 +108,12 @@
>  #define VRR_VSYNC_START_MASK			REG_GENMASK(12, 0)
>  #define
> VRR_VSYNC_START(vsync_start)		REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
>  
> +/* Common register for HDMI EMP and DP AS SDP */
> +#define _EMP_AS_SDP_TL_A			0x60204
> +#define EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
> +#define EMP_AS_SDP_TL(dev_priv,
> trans)		_MMIO_TRANS2(dev_priv, trans, _EMP_AS_SDP_TL_A)
> +#define
> EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK,(db_transmit_line))
> +
>  /*CMRR Registers*/
>  
>  #define _TRANS_CMRR_M_LO_A			0x604F0