[PATCH 11/12] drm/i915/flipq: Add intel_flipq_dump()

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: intel-xe at lists.freedesktop.org
> Subject: [PATCH 11/12] drm/i915/flipq: Add intel_flipq_dump()
> 
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Add a function for dumping the entries of a specific flip queue.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_flipq.c | 46 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_flipq.h |  2 +
>  2 files changed, 48 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c
> b/drivers/gpu/drm/i915/display/intel_flipq.c
> index fdda8d71c182..82a7996e7005 100644
> --- a/drivers/gpu/drm/i915/display/intel_flipq.c
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -147,6 +147,52 @@ static void intel_flipq_sw_dmc_wake(struct intel_crtc
> *crtc)
>  	intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe),
> PIPEDMC_SW_DMC_WAKE);  }
> 
> +void intel_flipq_dump(struct intel_crtc *crtc,
> +		      enum intel_flipq_id flipq_id)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +	u32 tmp;
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] FQ %d @ 0x%x: ",
> +		    crtc->base.base.id, crtc->base.name, flipq_id,
> +		    flipq->start_mmioaddr);
> +	for (int i = 0 ; i < intel_flipq_size_dw(flipq_id); i++) {
> +		printk(KERN_CONT " 0x%08x",
> +		       intel_de_read(display, PIPEDMC_FQ_RAM(flipq-
> >start_mmioaddr, i)));
> +		if (i % intel_flipq_elem_size_dw(flipq_id) ==
> intel_flipq_elem_size_dw(flipq_id) - 1)
> +			printk(KERN_CONT "\n");
> +	}
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] FQ %d: chp=0x%x, hp=0x%x\n",
> +		    crtc->base.base.id, crtc->base.name, flipq_id,
> +		    intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe,
> flipq_id)),
> +		    intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe,
> flipq_id)));
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] FQ %d: current head %d\n",
> +		    crtc->base.base.id, crtc->base.name, flipq_id,
> +		    intel_flipq_current_head(crtc, flipq_id));
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] flip queue timestamp: 0x%x\n",
> +		    crtc->base.base.id, crtc->base.name,
> +		    intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));
> +
> +	tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] flip queue atomic tails: P3 %d, P2 %d, P1 %d, G
> %d, F %d\n",
> +		    crtc->base.base.id, crtc->base.name,
> +		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp)); }
> +
>  static int cdclk_factor(struct intel_display *display)  {
>  	if (DISPLAY_VER(display) >= 30)
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.h
> b/drivers/gpu/drm/i915/display/intel_flipq.h
> index 8483c93ecdb3..0179719df8a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_flipq.h
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.h
> @@ -27,6 +27,8 @@ void intel_flipq_add(struct intel_crtc *crtc,
>  		     unsigned int pts,
>  		     enum intel_dsb_id dsb_id,
>  		     struct intel_dsb *dsb);
> +void intel_flipq_dump(struct intel_crtc *crtc,
> +		      enum intel_flipq_id flip_queue_id);
>  void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb);  void
> intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc);
> 
> --
> 2.49.0