[PATCH 04/11] drm/i915/alpm: Write PR_ALPM_CTL register

[Nautiyal, Ankit K]

On 5/2/2025 2:28 PM, Jouni Högander wrote:
> PR_ALPM_CTL register contains configurations related to Adaptive sync
> sdp. Configure these if Adaptive Sync SDP is supported.
>
> Bspec: 71014
> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_alpm.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 1bf08b80c23f9..5e5bc91ca7b76 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -348,6 +348,18 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>   			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
>   			ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
>   
> +		if (intel_dp->as_sdp_supported) {
> +			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +
> +			if (intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)

Can use pr_dpcd [DP_PANEL_REPLAY_CAPABILITY - 
DP_PANEL_REPLAY_CAP_SUPPORT] to avoid hardcoded index.


> +				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> +			if (!(intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))

Same as above.

Apart from the above, patch looks good to me.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

> +				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> +
> +			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
> +				       pr_alpm_ctl);
> +		}
> +
>   		intel_de_write(display,
>   			       PORT_ALPM_CTL(port),
>   			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |