[PATCH 07/11] drm/i915/alpm: Move port alpm configuration
Hogander, Jouni
jouni.hogander at intel.com
Tue May 20 16:59:15 UTC 2025
On Tue, 2025-05-20 at 14:30 +0530, Nautiyal, Ankit K wrote:
>
> On 5/2/2025 2:28 PM, Jouni Högander wrote:
> > It is specified in Bspec where port alpm configuration is supposed
> > to be
> > performed. Change accordingly.
> >
> > HAS: 14012758795
> Lets drop references to HAS and add Bspec: 68849
I have changed this.
> > Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 53 +++++++++++++--
> > -----
> > drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1 +
> > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++
> > 4 files changed, 44 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 4a8d4b34fa89e..857ce83075d8d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -344,7 +344,6 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp,
> > {
> > struct intel_display *display =
> > to_intel_display(intel_dp);
> > enum transcoder cpu_transcoder = crtc_state-
> > >cpu_transcoder;
> > - enum port port = dp_to_dig_port(intel_dp)->base.port;
> > u32 alpm_ctl;
> >
> > if (DISPLAY_VER(display) < 20 ||
> > (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> > @@ -374,23 +373,6 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp,
> > pr_alpm_ctl);
> > }
> >
> > - intel_de_write(display,
> > - PORT_ALPM_CTL(port),
> > - PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE
> > |
> > -
> > PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> > - PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0)
> > |
> > - PORT_ALPM_CTL_SILENCE_PERIOD(
> > - intel_dp-
> > >alpm_parameters.silence_period_sym_clocks));
> > -
> > - intel_de_write(display,
> > - PORT_ALPM_LFPS_CTL(port),
> > -
> > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> > -
> > PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
> > - intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > -
> > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
> > - intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > -
> > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
> > - intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms));
> > } else {
> > alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> > ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp-
> > >alpm_parameters.fast_wake_lines);
> > @@ -414,6 +396,41 @@ void intel_alpm_configure(struct intel_dp
> > *intel_dp,
> > intel_dp->alpm_parameters.transcoder = crtc_state-
> > >cpu_transcoder;
> > }
> >
> > +/**
> > + * intel_alpm_port_configure - Port ALPM configuration
> > + * @intel_dp: Intel DP
> > + * @crtc_state: CRTC state
> > + *
> > + * Perfrom port ALPM configuration based on crtc_state setup. This
> > is called as
> > + * a part of link training preparation.
> > + */
> > +void intel_alpm_port_configure(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state)
> > +{
> > + struct intel_display *display =
> > to_intel_display(intel_dp);
> > + enum port port = dp_to_dig_port(intel_dp)->base.port;
> > + u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
> > +
> > + if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> > + alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE
> > |
> > + PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> > + PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> > + PORT_ALPM_CTL_SILENCE_PERIOD(
> > + intel_dp-
> > >alpm_parameters.silence_period_sym_clocks);
> > + lfps_ctl_val =
> > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> > + PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATIO
> > N(
> > + intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > + PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_D
> > URATION(
> > + intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms) |
> > + PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DU
> > RATION(
> > + intel_dp-
> > >alpm_parameters.lfps_half_cycle_num_of_syms);
> > + }
> > +
> > + intel_de_write(display, PORT_ALPM_CTL(port),
> > alpm_ctl_val);
> > +
> > + intel_de_write(display, PORT_ALPM_LFPS_CTL(port),
> > lfps_ctl_val);
> > +}
> > +
> > void intel_alpm_pre_plane_update(struct intel_atomic_state
> > *state,
> > struct intel_crtc *crtc)
> > {
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index 83bbe0b7ff100..c9ddb2113fe0d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -25,6 +25,8 @@ void intel_alpm_configure(struct intel_dp
> > *intel_dp,
> > const struct intel_crtc_state
> > *crtc_state);
> > void intel_alpm_pre_plane_update(struct intel_atomic_state
> > *state,
> > struct intel_crtc *crtc);
> > +void intel_alpm_port_configure(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state);
> > void intel_alpm_post_plane_update(struct intel_atomic_state
> > *state,
> > struct intel_crtc *crtc);
> > void intel_alpm_lobf_debugfs_add(struct intel_connector
> > *connector);
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index b09f724c3046b..1318886e34dd7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -10,6 +10,7 @@
> >
> > #include "i915_reg.h"
> > #include "i915_utils.h"
> > +#include "intel_alpm.h"
> > #include "intel_cx0_phy.h"
> > #include "intel_cx0_phy_regs.h"
> > #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 74132c1d63858..ce7a4765b10ea 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3743,6 +3743,12 @@ static void
> > mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> >
> > intel_ddi_buf_enable(encoder, intel_dp->DP);
> > intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > +
> > + /*
> > + * 6.k If AUX-Less ALPM is going to be enabled
> > + * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL
> > here
> > + */
> > + intel_alpm_port_configure(intel_dp, crtc_state);
>
> I think we should add a check to ensure this code runs only on LNL+
> platforms (which supports ALPM).
>
> Otherwise, we might end up writing
> > PORT_ALPM_CTL|and|PORT_ALPM_LFPS_CTL| that are not defined on
> > earlier
> platforms, which could lead to unintended behavior.
You are right. I have added display version check in recent version.
Thank you for pointing this out.
BR,
Jouni Högander
>
> Regards,
>
> Ankit
>
> > }
> >
> > static void intel_ddi_prepare_link_retrain(struct intel_dp
> > *intel_dp,
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