[PATCH v10 03/10] mtd: intel-dg: implement access functions

Usyskin, Alexander alexander.usyskin at intel.com
Wed May 21 09:19:36 UTC 2025


> Subject: Re: [PATCH v10 03/10] mtd: intel-dg: implement access functions
> 
> On Thu, May 15, 2025 at 04:33:38PM +0300, Alexander Usyskin wrote:
> > Implement read(), erase() and write() functions.
> 
> ...
> 
> > +__maybe_unused
> > +static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm,
> loff_t from)
> > +{
> > +	unsigned int i;
> > +
> > +	for (i = 0; i < nvm->nregions; i++) {
> > +		if ((nvm->regions[i].offset + nvm->regions[i].size - 1) > from
> &&
> 
> Since it's already off by one, I'm wondering if this should be >= ?
> 
Yep, will fix


> > +		    nvm->regions[i].offset <= from &&
> > +		    nvm->regions[i].size != 0)
> > +			break;
> > +	}
> > +
> > +	return i;
> > +}
> 
> ...
> 
> > +__maybe_unused
> > +static ssize_t
> > +idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64
> *fail_addr)
> > +{
> > +	u64 i;
> > +	const u32 block = 0x10;
> > +	void __iomem *base = nvm->base;
> 
> Reverse xmas order (along with all other places).
Will do
> 
> > +	for (i = 0; i < len; i += SZ_4K) {
> > +		iowrite32(from + i, base + NVM_ADDRESS_REG);
> > +		iowrite32(region << 24 | block, base + NVM_ERASE_REG);
> > +		/* Since the writes are via sguint
> 
> sguint?

Sgunit, I suppose - will fix

> 
> > +		 * we cannot do back to back erases.
> > +		 */
> > +		msleep(50);
> > +	}
> > +	return len;
> > +}
> 
> Raag


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