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<div class="moz-cite-prefix">On 05/05/2016 15:02, Antoine, Peter
wrote:<br>
</div>
<blockquote
cite="mid:C182EC90AE29B54BB712270726FAFA7514583F4D@IRSMSX102.ger.corp.intel.com"
type="cite">
<pre wrap="">The attached version still does not explain that the WOPCM_TOP is to tell the GuC not to use that space.</pre>
</blockquote>
<small><br>
That's NOT what WOPCM_TOP means. The GuC is allowed to use the
space up to the value stored in the GUC_WOPCM_SIZE register (as
the comment above the #define says). Architecturally, this is
allowed to be any value greater than (16K+sizeof internal SRAM
(64, 128, or 256K)) and less than or equal to GUC_WOPCM_TOP (which
is a platform-independent constant), so we normally choose the
maximm allowed. Howver on BXT, we need to leave some space at the
top for the RC6 image, hence the logic (and comments!) in
guc_wopcm_size().<br>
<br>
</small>
<blockquote
cite="mid:C182EC90AE29B54BB712270726FAFA7514583F4D@IRSMSX102.ger.corp.intel.com"
type="cite">
<pre wrap="">
The extra information does not aid anybody as the information is used internally within the GuC.</pre>
</blockquote>
<small>It may help the next person who has to figure out what's gone
wrong on some future chip that needs more than 64K for RC6!</small><br>
<br>
<small>.Dave.</small><br>
<blockquote
cite="mid:C182EC90AE29B54BB712270726FAFA7514583F4D@IRSMSX102.ger.corp.intel.com"
type="cite">
<pre wrap="">
But, I have not actual objection to the patch.
Peter.
</pre>
</blockquote>
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