[ 0.000000] Linux version 4.6.0-rc6+intel-drm-nightly (stefan@kant) (gcc version 5.3.0 (Gentoo 5.3.0 p1.0, pie-0.6.5) ) #3 SMP PREEMPT Sun May 8 12:36:26 CEST 2016 [ 0.000000] Command line: BOOT_IMAGE=/vmlinuz-4.6.0-rc6+intel-drm-nightly root=/dev/sda4 ro rootflags=subvol=@ drm.debug=0xe # ... [ 82.259722] kms_frontbuffer_tracking: executing [ 82.262264] [drm:i915_gem_open] [ 82.262743] [drm:i915_gem_open] [ 82.262940] [drm:drm_mode_addfb2] [FB:79] [ 82.262953] [drm:drm_mode_addfb2] [FB:80] [ 82.262969] [drm:drm_mode_addfb2] [FB:81] [ 82.262984] [drm:drm_mode_addfb2] [FB:82] [ 82.263007] [drm:drm_mode_addfb2] [FB:83] [ 82.263449] kms_frontbuffer_tracking: starting subtest fbc-1p-primscrn-spr-indfb-fullscreen [ 82.263488] Setting dangerous option i915.enable_fbc - tainting kernel [ 82.263504] Setting dangerous option i915.enable_psr - tainting kernel [ 82.263577] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 82.271459] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 82.271467] [drm:intel_disable_pipe] disabling pipe A [ 82.289945] [drm:__intel_fbc_disable] Disabling FBC on pipe A [ 82.289949] [drm:intel_disable_shared_dpll] disable LCPLL 1350 (active 1, on? 1) for crtc 26 [ 82.289950] [drm:intel_disable_shared_dpll] disabling LCPLL 1350 [ 82.289954] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 82.289956] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 82.289957] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 82.289958] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 82.289959] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 82.289960] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 82.289961] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 82.289962] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 82.289962] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 82.289963] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 82.289964] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 82.289965] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 82.289966] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 82.289967] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 82.289968] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 82.289969] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 82.289971] [drm:verify_single_dpll_state] WRPLL 1 [ 82.289972] [drm:verify_single_dpll_state] WRPLL 2 [ 82.289973] [drm:verify_single_dpll_state] SPLL [ 82.289974] [drm:verify_single_dpll_state] LCPLL 810 [ 82.289975] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.289975] [drm:verify_single_dpll_state] LCPLL 2700 [ 82.289979] [drm:intel_power_well_disable] disabling display [ 82.289980] [drm:hsw_set_power_well] Requesting to disable the power well [ 82.289983] [drm:verify_crtc_state] [CRTC:26] [ 82.289985] [drm:intel_power_well_disable] disabling always-on [ 82.290002] [drm:drm_mode_setcrtc] [CRTC:30:crtc-1] [ 82.290014] [drm:drm_mode_setcrtc] [CRTC:34:crtc-2] [ 82.290062] [drm:drm_mode_addfb2] [FB:77] [ 82.295511] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 82.295515] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1] [ 82.295523] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains [ 82.295524] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 30 [ 82.295526] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 241500KHz [ 82.295529] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 30 [ 82.295529] [drm:intel_dp_compute_config] DP link bw required 724500 available 864000 [ 82.295530] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 30, dithering: 0 [ 82.295532] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8807f6729000 for pipe A [ 82.295533] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 82.295533] [drm:intel_dump_pipe_config] pipe bpp: 30, dithering: 0 [ 82.295534] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 82.295535] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 7034197, gmch_n: 8388608, link_m: 468946, link_n: 524288, tu: 64 [ 82.295536] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 82.295536] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 82.295537] [drm:intel_dump_pipe_config] requested mode: [ 82.295538] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 82.295539] [drm:intel_dump_pipe_config] adjusted mode: [ 82.295540] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 82.295541] [drm:intel_dump_crtc_timings] crtc timings: 241500 2560 2608 2640 2720 1440 1443 1448 1481, type: 0x48 flags: 0x9 [ 82.295542] [drm:intel_dump_pipe_config] port clock: 270000 [ 82.295542] [drm:intel_dump_pipe_config] pipe src size: 2560x1440 [ 82.295543] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 82.295544] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 82.295544] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 82.295545] [drm:intel_dump_pipe_config] ips: 0 [ 82.295545] [drm:intel_dump_pipe_config] double wide: 0 [ 82.295546] [drm:intel_dump_pipe_config] ddi_pll_sel: 0x20000000; dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 82.295547] [drm:intel_dump_pipe_config] planes on this crtc [ 82.295548] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 82.295549] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 82.295550] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 82.295553] [drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A [ 82.299058] [drm:intel_power_well_enable] enabling always-on [ 82.299060] [drm:intel_power_well_enable] enabling display [ 82.299061] [drm:hsw_set_power_well] Enabling power well [ 82.301100] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 82.301103] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 82.301104] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 82.301105] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 82.301105] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 82.301106] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 82.301107] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 82.301108] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 82.301108] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 82.301109] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 82.301110] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 82.301111] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 82.301112] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 82.301113] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 82.301114] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 82.301115] [drm:verify_single_dpll_state] WRPLL 1 [ 82.301116] [drm:verify_single_dpll_state] WRPLL 2 [ 82.301117] [drm:verify_single_dpll_state] SPLL [ 82.301118] [drm:verify_single_dpll_state] LCPLL 810 [ 82.301119] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.301119] [drm:verify_single_dpll_state] LCPLL 2700 [ 82.301121] [drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 26 [ 82.301121] [drm:intel_enable_shared_dpll] enabling LCPLL 1350 [ 82.302194] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 82.302196] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 82.302196] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 82.302822] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 82.305771] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 82.305952] [drm:intel_enable_pipe] enabling pipe A [ 82.305987] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38] [ 82.305988] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 82.322737] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 82.322742] [drm:verify_crtc_state] [CRTC:26] [ 82.322750] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.322779] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 82.372829] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 82.389486] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 82.406126] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 82.406132] [drm:intel_disable_pipe] disabling pipe A [ 82.423956] [drm:intel_disable_shared_dpll] disable LCPLL 1350 (active 1, on? 1) for crtc 26 [ 82.423958] [drm:intel_disable_shared_dpll] disabling LCPLL 1350 [ 82.423961] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 82.423964] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 82.423965] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 82.423965] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 82.423966] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 82.423967] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 82.423968] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 82.423969] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 82.423969] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 82.423970] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 82.423971] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 82.423972] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 82.423973] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 82.423974] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 82.423975] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 82.423976] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 82.423977] [drm:verify_single_dpll_state] WRPLL 1 [ 82.423978] [drm:verify_single_dpll_state] WRPLL 2 [ 82.423979] [drm:verify_single_dpll_state] SPLL [ 82.423980] [drm:verify_single_dpll_state] LCPLL 810 [ 82.423981] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.423982] [drm:verify_single_dpll_state] LCPLL 2700 [ 82.423985] [drm:intel_power_well_disable] disabling display [ 82.423986] [drm:hsw_set_power_well] Requesting to disable the power well [ 82.423989] [drm:verify_crtc_state] [CRTC:26] [ 82.423990] [drm:intel_power_well_disable] disabling always-on [ 82.424004] [drm:drm_mode_setcrtc] [CRTC:30:crtc-1] [ 82.424014] [drm:drm_mode_setcrtc] [CRTC:34:crtc-2] [ 82.425073] [drm:drm_mode_addfb2] [FB:77] [ 82.481237] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 82.481242] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1] [ 82.481250] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains [ 82.481251] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 30 [ 82.481253] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 241500KHz [ 82.481256] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 30 [ 82.481257] [drm:intel_dp_compute_config] DP link bw required 724500 available 864000 [ 82.481258] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 30, dithering: 0 [ 82.481259] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8807f6728000 for pipe A [ 82.481260] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 82.481261] [drm:intel_dump_pipe_config] pipe bpp: 30, dithering: 0 [ 82.481262] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 82.481263] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 7034197, gmch_n: 8388608, link_m: 468946, link_n: 524288, tu: 64 [ 82.481263] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 82.481264] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 82.481265] [drm:intel_dump_pipe_config] requested mode: [ 82.481266] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 82.481267] [drm:intel_dump_pipe_config] adjusted mode: [ 82.481268] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 82.481269] [drm:intel_dump_crtc_timings] crtc timings: 241500 2560 2608 2640 2720 1440 1443 1448 1481, type: 0x48 flags: 0x9 [ 82.481269] [drm:intel_dump_pipe_config] port clock: 270000 [ 82.481270] [drm:intel_dump_pipe_config] pipe src size: 2560x1440 [ 82.481271] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 82.481271] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 82.481272] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 82.481273] [drm:intel_dump_pipe_config] ips: 0 [ 82.481273] [drm:intel_dump_pipe_config] double wide: 0 [ 82.481274] [drm:intel_dump_pipe_config] ddi_pll_sel: 0x20000000; dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 82.481275] [drm:intel_dump_pipe_config] planes on this crtc [ 82.481275] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 82.481276] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 82.481277] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 82.481282] [drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A [ 82.487311] [drm:intel_power_well_enable] enabling always-on [ 82.487313] [drm:intel_power_well_enable] enabling display [ 82.487314] [drm:hsw_set_power_well] Enabling power well [ 82.488383] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 82.488385] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 82.488386] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 82.488387] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 82.488388] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 82.488388] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 82.488389] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 82.488390] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 82.488391] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 82.488392] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 82.488393] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 82.488394] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 82.488395] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 82.488396] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 82.488397] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 82.488398] [drm:verify_single_dpll_state] WRPLL 1 [ 82.488399] [drm:verify_single_dpll_state] WRPLL 2 [ 82.488400] [drm:verify_single_dpll_state] SPLL [ 82.488401] [drm:verify_single_dpll_state] LCPLL 810 [ 82.488401] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.488402] [drm:verify_single_dpll_state] LCPLL 2700 [ 82.488403] [drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 26 [ 82.488404] [drm:intel_enable_shared_dpll] enabling LCPLL 1350 [ 82.489480] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 82.489481] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 82.489481] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 82.490098] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 82.492379] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 82.492561] [drm:intel_enable_pipe] enabling pipe A [ 82.492589] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38] [ 82.492591] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 82.509336] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 82.509341] [drm:verify_crtc_state] [CRTC:26] [ 82.509361] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.509390] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 82.559436] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 82.576086] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 82.592732] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 82.592738] [drm:intel_disable_pipe] disabling pipe A [ 82.610935] [drm:intel_disable_shared_dpll] disable LCPLL 1350 (active 1, on? 1) for crtc 26 [ 82.610938] [drm:intel_disable_shared_dpll] disabling LCPLL 1350 [ 82.610942] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 82.610944] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 82.610945] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 82.610946] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 82.610946] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 82.610947] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 82.610948] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 82.610949] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 82.610950] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 82.610950] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 82.610951] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 82.610952] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 82.610953] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 82.610954] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 82.610955] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 82.610957] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 82.610958] [drm:verify_single_dpll_state] WRPLL 1 [ 82.610959] [drm:verify_single_dpll_state] WRPLL 2 [ 82.610960] [drm:verify_single_dpll_state] SPLL [ 82.610961] [drm:verify_single_dpll_state] LCPLL 810 [ 82.610961] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.610962] [drm:verify_single_dpll_state] LCPLL 2700 [ 82.610965] [drm:intel_power_well_disable] disabling display [ 82.610967] [drm:hsw_set_power_well] Requesting to disable the power well [ 82.610969] [drm:verify_crtc_state] [CRTC:26] [ 82.610971] [drm:intel_power_well_disable] disabling always-on [ 82.610985] [drm:drm_mode_setcrtc] [CRTC:30:crtc-1] [ 82.610995] [drm:drm_mode_setcrtc] [CRTC:34:crtc-2] [ 82.611902] Setting dangerous option i915.enable_fbc - tainting kernel [ 82.635598] [drm:drm_mode_setcrtc] [CRTC:26:crtc-0] [ 82.635602] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1] [ 82.635612] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains [ 82.635612] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 30 [ 82.635614] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 241500KHz [ 82.635618] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 30 [ 82.635618] [drm:intel_dp_compute_config] DP link bw required 724500 available 864000 [ 82.635619] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 30, dithering: 0 [ 82.635621] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8807f672b000 for pipe A [ 82.635621] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 82.635622] [drm:intel_dump_pipe_config] pipe bpp: 30, dithering: 0 [ 82.635623] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 82.635624] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 7034197, gmch_n: 8388608, link_m: 468946, link_n: 524288, tu: 64 [ 82.635625] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 82.635625] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 82.635626] [drm:intel_dump_pipe_config] requested mode: [ 82.635627] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 82.635628] [drm:intel_dump_pipe_config] adjusted mode: [ 82.635629] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 82.635630] [drm:intel_dump_crtc_timings] crtc timings: 241500 2560 2608 2640 2720 1440 1443 1448 1481, type: 0x48 flags: 0x9 [ 82.635631] [drm:intel_dump_pipe_config] port clock: 270000 [ 82.635631] [drm:intel_dump_pipe_config] pipe src size: 2560x1440 [ 82.635632] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 82.635633] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 82.635633] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 82.635634] [drm:intel_dump_pipe_config] ips: 0 [ 82.635634] [drm:intel_dump_pipe_config] double wide: 0 [ 82.635635] [drm:intel_dump_pipe_config] ddi_pll_sel: 0x20000000; dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 82.635636] [drm:intel_dump_pipe_config] planes on this crtc [ 82.635637] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 82.635638] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 82.635639] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 82.635643] [drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A [ 82.641161] [drm:intel_power_well_enable] enabling always-on [ 82.641163] [drm:intel_power_well_enable] enabling display [ 82.641164] [drm:hsw_set_power_well] Enabling power well [ 82.642380] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 82.642383] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 82.642384] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 82.642385] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 82.642385] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 82.642386] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 82.642387] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 82.642388] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 82.642388] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 82.642389] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 82.642390] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 82.642391] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 82.642392] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 82.642393] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 82.642394] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 82.642396] [drm:verify_single_dpll_state] WRPLL 1 [ 82.642396] [drm:verify_single_dpll_state] WRPLL 2 [ 82.642397] [drm:verify_single_dpll_state] SPLL [ 82.642398] [drm:verify_single_dpll_state] LCPLL 810 [ 82.642399] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.642399] [drm:verify_single_dpll_state] LCPLL 2700 [ 82.642401] [drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 26 [ 82.642402] [drm:intel_enable_shared_dpll] enabling LCPLL 1350 [ 82.643477] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 82.643477] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 82.643478] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 82.644094] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 82.646379] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 82.646560] [drm:intel_enable_pipe] enabling pipe A [ 82.646586] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38] [ 82.646587] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 82.646591] [drm:intel_fbc_alloc_cfb] reserved 14745600 bytes of contiguous stolen space for FBC, threshold: 1 [ 82.646592] [drm:intel_fbc_enable] Enabling FBC on pipe A [ 82.663339] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 82.663352] [drm:verify_crtc_state] [CRTC:26] [ 82.663360] [drm:verify_single_dpll_state] LCPLL 1350 [ 82.663390] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 82.713428] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 82.730166] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 82.780157] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 82.830157] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 82.880235] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 82.896946] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 82.946957] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 82.963628] [drm:drm_mode_addfb2] [FB:77] [ 82.980281] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 83.030345] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 83.047065] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 83.097060] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 83.147083] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 83.197163] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 83.213873] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf [ 83.263884] [drm:pipe_crc_set_source] stopping CRCs for pipe A [ 83.297177] [drm:hsw_audio_codec_disable] Disable audio codec on pipe A [ 83.297183] [drm:intel_disable_pipe] disabling pipe A [ 83.314929] [drm:__intel_fbc_disable] Disabling FBC on pipe A [ 83.314933] [drm:intel_disable_shared_dpll] disable LCPLL 1350 (active 1, on? 1) for crtc 26 [ 83.314934] [drm:intel_disable_shared_dpll] disabling LCPLL 1350 [ 83.314937] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 83.314940] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 83.314941] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 83.314941] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 83.314942] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 83.314943] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 83.314944] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 83.314945] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 83.314945] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 83.314946] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 83.314947] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 83.314948] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 83.314949] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 83.314950] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 83.314951] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 83.314952] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 83.314953] [drm:verify_single_dpll_state] WRPLL 1 [ 83.314954] [drm:verify_single_dpll_state] WRPLL 2 [ 83.314955] [drm:verify_single_dpll_state] SPLL [ 83.314956] [drm:verify_single_dpll_state] LCPLL 810 [ 83.314957] [drm:verify_single_dpll_state] LCPLL 1350 [ 83.314958] [drm:verify_single_dpll_state] LCPLL 2700 [ 83.314961] [drm:intel_power_well_disable] disabling display [ 83.314963] [drm:hsw_set_power_well] Requesting to disable the power well [ 83.314965] [drm:verify_crtc_state] [CRTC:26] [ 83.314966] [drm:intel_power_well_disable] disabling always-on [ 83.315917] kms_frontbuffer_tracking: exiting, ret=0 [ 83.315942] Setting dangerous option i915.enable_psr - tainting kernel [ 83.315945] Setting dangerous option i915.enable_fbc - tainting kernel [ 83.315984] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains [ 83.315985] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 30 [ 83.315986] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 241500KHz [ 83.315989] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 30 [ 83.315990] [drm:intel_dp_compute_config] DP link bw required 724500 available 864000 [ 83.315991] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 30, dithering: 0 [ 83.315992] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff8807f45ce800 for pipe A [ 83.315992] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 83.315993] [drm:intel_dump_pipe_config] pipe bpp: 30, dithering: 0 [ 83.315993] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 83.315994] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 7034197, gmch_n: 8388608, link_m: 468946, link_n: 524288, tu: 64 [ 83.315995] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 83.315995] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0 [ 83.315996] [drm:intel_dump_pipe_config] requested mode: [ 83.315997] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 83.315997] [drm:intel_dump_pipe_config] adjusted mode: [ 83.315998] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9 [ 83.315999] [drm:intel_dump_crtc_timings] crtc timings: 241500 2560 2608 2640 2720 1440 1443 1448 1481, type: 0x48 flags: 0x9 [ 83.316000] [drm:intel_dump_pipe_config] port clock: 270000 [ 83.316000] [drm:intel_dump_pipe_config] pipe src size: 2560x1440 [ 83.316000] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [ 83.316001] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 83.316002] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 83.316002] [drm:intel_dump_pipe_config] ips: 0 [ 83.316002] [drm:intel_dump_pipe_config] double wide: 0 [ 83.316003] [drm:intel_dump_pipe_config] ddi_pll_sel: 0x20000000; dpll_hw_state: wrpll: 0x0 spll: 0x0 [ 83.316003] [drm:intel_dump_pipe_config] planes on this crtc [ 83.316004] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 disabled, scaler_id = 0 [ 83.316004] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [ 83.316005] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [ 83.316008] [drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A [ 83.316014] [drm:intel_power_well_enable] enabling always-on [ 83.316015] [drm:intel_power_well_enable] enabling display [ 83.316016] [drm:hsw_set_power_well] Enabling power well [ 83.317357] [drm:verify_encoder_state] [ENCODER:37:DAC-37] [ 83.317358] [drm:verify_encoder_state] [ENCODER:38:TMDS-38] [ 83.317359] [drm:verify_encoder_state] [ENCODER:40:DP MST-40] [ 83.317359] [drm:verify_encoder_state] [ENCODER:41:DP MST-41] [ 83.317360] [drm:verify_encoder_state] [ENCODER:42:DP MST-42] [ 83.317360] [drm:verify_encoder_state] [ENCODER:47:TMDS-47] [ 83.317360] [drm:verify_encoder_state] [ENCODER:49:TMDS-49] [ 83.317361] [drm:verify_encoder_state] [ENCODER:51:DP MST-51] [ 83.317361] [drm:verify_encoder_state] [ENCODER:52:DP MST-52] [ 83.317362] [drm:verify_encoder_state] [ENCODER:53:DP MST-53] [ 83.317362] [drm:intel_connector_verify_state] [CONNECTOR:36:VGA-1] [ 83.317363] [drm:intel_connector_verify_state] [CONNECTOR:45:HDMI-A-1] [ 83.317363] [drm:intel_connector_verify_state] [CONNECTOR:48:HDMI-A-2] [ 83.317364] [drm:intel_connector_verify_state] [CONNECTOR:50:DP-2] [ 83.317365] [drm:intel_connector_verify_state] [CONNECTOR:54:HDMI-A-3] [ 83.317365] [drm:verify_single_dpll_state] WRPLL 1 [ 83.317366] [drm:verify_single_dpll_state] WRPLL 2 [ 83.317366] [drm:verify_single_dpll_state] SPLL [ 83.317367] [drm:verify_single_dpll_state] LCPLL 810 [ 83.317367] [drm:verify_single_dpll_state] LCPLL 1350 [ 83.317368] [drm:verify_single_dpll_state] LCPLL 2700 [ 83.317369] [drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 26 [ 83.317369] [drm:intel_enable_shared_dpll] enabling LCPLL 1350 [ 83.318434] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 83.318434] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 83.318435] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 83.319047] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [ 83.321368] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [ 83.321548] [drm:intel_enable_pipe] enabling pipe A [ 83.321570] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38] [ 83.321571] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD [ 83.321574] [drm:intel_fbc_alloc_cfb] reserved 14745600 bytes of contiguous stolen space for FBC, threshold: 1 [ 83.321575] [drm:intel_fbc_enable] Enabling FBC on pipe A [ 83.338349] [drm:intel_connector_verify_state] [CONNECTOR:39:DP-1] [ 83.338353] [drm:verify_crtc_state] [CRTC:26] [ 83.338360] [drm:verify_single_dpll_state] LCPLL 1350