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<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I am executing the DP compliance test suite and the only test currently failing with the drm-tip + my patch (<a href="https://patchwork.freedesktop.org/series/25191/">https://patchwork.freedesktop.org/series/25191/</a>)<o:p></o:p></p>
<p class="MsoNormal">Is the power management test (4.4.3) where it expects the source DUT to go into Power state D3 by setting DPCD register 0x600 to 2 as requested by the test GUI and then exit to normal operation by writing 1 to that DPCD register.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I see that in the code intel_dp_sink_dpms() with DPMS_OFF will set that register to 2 and then with DPMS on it sets it to 1, but since that happens only during encoder disable and enable, I am not sure how it will happen through this test.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Any thoughts? Please refer to the section 4.4.3 in the CTS spec.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span style="font-family:"Brush Script MT"">Regards<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Berlin Sans FB",sans-serif">Manasi Navare<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Berlin Sans FB",sans-serif">Graphics Kernel Developer<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Berlin Sans FB",sans-serif">OTC, Intel Corporation<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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