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<div class="moz-cite-prefix">On Monday 25 September 2017 02:00 PM,
Jani Nikula wrote:<br>
</div>
<blockquote cite="mid:87bmlz5gfn.fsf@nikula.org" type="cite">
<pre wrap="">On Sat, 23 Sep 2017, vathsala nagaraju <a class="moz-txt-link-rfc2396E" href="mailto:vathsala.nagaraju@intel.com"><vathsala.nagaraju@intel.com></a> wrote:
</pre>
<blockquote type="cite">
<pre wrap="">Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
v3 : (Rodrigo)
- move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
- replace with &=
Cc: Rodrigo Vivi <a class="moz-txt-link-rfc2396E" href="mailto:rodrigo.vivi@intel.com"><rodrigo.vivi@intel.com></a>
CC: Puthikorn Voravootivat <a class="moz-txt-link-rfc2396E" href="mailto:puthik@chromium.org"><puthik@chromium.org></a>
Reviewed-by: Rodrigo Vivi <a class="moz-txt-link-rfc2396E" href="mailto:rodrigo.vivi@intel.com"><rodrigo.vivi@intel.com></a>
Signed-off-by: Vathsala Nagaraju <a class="moz-txt-link-rfc2396E" href="mailto:vathsala.nagaraju@intel.com"><vathsala.nagaraju@intel.com></a>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..b880c84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4047,7 +4047,7 @@ enum {
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
#define EDP_PSR2_IDLE_MASK 0xf
-#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
</pre>
</blockquote>
<pre wrap="">
In the register definitions we use the shift values directly, not the
macro. That's the style we've adopted. Please stick to it.</pre>
</blockquote>
<small>Macro was suggested by Rodrigo. </small><br>
<blockquote cite="mid:87bmlz5gfn.fsf@nikula.org" type="cite">
<pre wrap="">
Ditto for the indent, why do you remove it?</pre>
</blockquote>
BR,
Jani.
<blockquote cite="mid:87bmlz5gfn.fsf@nikula.org" type="cite">
<blockquote type="cite">
<pre wrap="">
#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..adf7abc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+ &sink_latency) == 1) {
+ sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
+ } else {
+ sink_latency = 0;
+ }
+ val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
</pre>
</blockquote>
<pre wrap="">
</pre>
</blockquote>
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