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<div class="moz-cite-prefix">On 09/11/17 14:06, Lionel Landwerlin
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:fc21a154-e708-e55e-2a2d-85dabbea2014@intel.com">
<blockquote type="cite" style="color: #000000;"><br>
+ } else if (INTEL_GEN(dev_priv) <= 9) {
<br>
+ u32 ctc_reg = I915_READ(GEN8_CTC_MODE);
<br>
+ u64 freq = 0;
<br>
+
<br>
+ if ((ctc_reg & GEN8_CTC_SOURCE_PARAMETER_MASK) ==
GEN8_CTC_SOURCE_DIVIDE_LOGIC)
<br>
+ freq =
read_timestamp_frequency_from_divide(dev_priv);
<br>
+ else
<br>
+ freq = IS_GEN9_LP(dev_priv) ? 19200000 : 24000000;
<br>
+
<br>
+ /* Now figure out how the command stream's timestamp
register
<br>
+ * increments from this frequency (it might increment
only
<br>
+ * every few clock cycle).
<br>
+ */
<br>
+ freq >>= 3 - ((ctc_reg &
GEN8_CTC_SHIFT_PARAMETER_MASK) >>
<br>
+ GEN8_CTC_SHIFT_PARAMETER_SHIFT);
<br>
</blockquote>
Gen8 documentation is indeed fuzzy. Are we getting 12.5mhz after
this shift as doc says it to have 80ns base.
</blockquote>
Forgot to answer that point. Let me check this on BDW again.<br>
But yes, the idea is that we should get 12.5MHz on BDW.<br>
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