<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> </head> <body text="#000000" bgcolor="#FFFFFF"> <div class="moz-cite-prefix">On 09/11/17 14:13, Lionel Landwerlin wrote: </div> <blockquote type="cite" cite="mid:1f1133de-734f-487e-6b66-779837c51594@intel.com"> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <div class="moz-cite-prefix">On 09/11/17 14:06, Lionel Landwerlin wrote: </div> <blockquote type="cite" cite="mid:fc21a154-e708-e55e-2a2d-85dabbea2014@intel.com"> <blockquote type="cite" style="color: #000000;"> + } else if (INTEL_GEN(dev_priv) <= 9) { + u32 ctc_reg = I915_READ(GEN8_CTC_MODE); + u64 freq = 0; + + if ((ctc_reg & GEN8_CTC_SOURCE_PARAMETER_MASK) == GEN8_CTC_SOURCE_DIVIDE_LOGIC) + freq = read_timestamp_frequency_from_divide(dev_priv); + else + freq = IS_GEN9_LP(dev_priv) ? 19200000 : 24000000; + + /* Now figure out how the command stream's timestamp register + * increments from this frequency (it might increment only + * every few clock cycle). + */ + freq >>= 3 - ((ctc_reg & GEN8_CTC_SHIFT_PARAMETER_MASK) >> + GEN8_CTC_SHIFT_PARAMETER_SHIFT); </blockquote> Gen8 documentation is indeed fuzzy. Are we getting 12.5mhz after this shift as doc says it to have 80ns base. </blockquote> Forgot to answer that point. Let me check this on BDW again. But yes, the idea is that we should get 12.5MHz on BDW.</blockquote> Okay, looks like that's wrong on my BDW system.... So this bit of right shift should probably only be applied to the else case (i.e. gen9) - Lionel </body> </html>