<div dir="ltr">Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jan 19, 2018 at 6:41 AM, Ville Syrjala <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a><wbr>><br>
<br>
Let's document why we claim hsub==8,vsub==16 for CCS.<br>
<br>
v2: Replace my explanation with Jason's<br>
<span class=""><br>
Cc: Daniel Vetter <<a href="mailto:daniel@ffwll.ch">daniel@ffwll.ch</a>><br>
Cc: Ben Widawsky <<a href="mailto:ben@bwidawsk.net">ben@bwidawsk.net</a>><br>
Cc: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br>
Cc: Daniel Stone <<a href="mailto:daniels@collabora.com">daniels@collabora.com</a>><br>
Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a><wbr>><br>
---<br>
</span> drivers/gpu/drm/i915/intel_<wbr>display.c | 14 ++++++++++++++<br>
1 file changed, 14 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/i915/intel_<wbr>display.c b/drivers/gpu/drm/i915/intel_<wbr>display.c<br>
index 91f3c0a64596..8d0d5d8753c0 100644<br>
--- a/drivers/gpu/drm/i915/intel_<wbr>display.c<br>
+++ b/drivers/gpu/drm/i915/intel_<wbr>display.c<br>
@@ -2387,6 +2387,20 @@ static unsigned int intel_fb_modifier_to_tiling(<wbr>uint64_t fb_modifier)<br>
}<br>
}<br>
<br>
+/*<br>
+ * From the Sky Lake PRM:<br>
+ * "The Color Control Surface (CCS) contains the compression status of<br>
+ * the cache-line pairs. The compression state of the cache-line pair<br>
+ * is specified by 2 bits in the CCS. Each CCS cache-line represents<br>
+ * an area on the main surface of 16 x16 sets of 128 byte Y-tiled<br>
+ * cache-line-pairs. CCS is always Y tiled."<br>
+ *<br>
+ * Since cache line pairs refers to horizontally adjacent cache lines,<br>
+ * each cache line in the CCS corresponds to an area of 32x16 cache<br>
+ * lines on the main surface. Since each pixel is 4 bytes, this gives<br>
+ * us a ratio of one byte in the CCS for each 8x16 pixels in the<br>
+ * main surface.<br>
<div class="HOEnZb"><div class="h5">+ */<br>
static const struct drm_format_info ccs_formats[] = {<br>
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },<br>
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },<br>
--<br>
2.13.6<br>
<br>
</div></div></blockquote></div><br></div>