<div dir="ltr"><div class="gmail_default" style="font-family:verdana,sans-serif;font-size:small"><br></div><br><div class="gmail_quote"><div dir="ltr">On Mon, Jul 30, 2018 at 5:07 AM Mika Kuoppala <<a href="mailto:mika.kuoppala@linux.intel.com">mika.kuoppala@linux.intel.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">The register for 0xe420 is unable to hold any value, including<br>
this bit. The documentation is also mixed between having a<br>
register bit for toggle and having a state command setup<br>
for it. Apparently the register toggle is deprecated.<br>
<br></blockquote><div> CACHE_MODE_SS is not listed in <div class="gmail_default" style="font-family:verdana,sans-serif;font-size:small;display:inline">a </div>gfxspecs table <div class="gmail_default" style="font-family:verdana,sans-serif;font-size:small;display:inline">which lists all</div> user mode</div><div> non-privileged registers. So, <div class="gmail_default" style="font-family:verdana,sans-serif;font-size:small;display:inline"></div><div class="gmail_default" style="font-family:verdana,sans-serif;font-size:small;display:inline">do you think </div>making any changes <div class="gmail_default" style="font-family:verdana,sans-serif;font-size:small;display:inline">to the register</div></div><div><div class="gmail_default" style="font-family:verdana,sans-serif;font-size:small;display:inline"> from mesa will hold?</div></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
Remove the register toggle as evidence shows it's futile.<br>
<br>
The thing remaining is an apology and humble request for<br>
Mesa folks to resurrect their state setup for this as they<br>
were on right track from start.<br>
<br>
This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.<br>
<br>
Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")<br>
References: HSDES#1406393558<br>
Cc: Oscar Mateo <<a href="mailto:oscar.mateo@intel.com" target="_blank">oscar.mateo@intel.com</a>><br>
Cc: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>><br>
Cc: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk" target="_blank">chris@chris-wilson.co.uk</a>><br>
Cc: Lionel Landwerlin <<a href="mailto:lionel.g.landwerlin@intel.com" target="_blank">lionel.g.landwerlin@intel.com</a>><br>
Signed-off-by: Mika Kuoppala <<a href="mailto:mika.kuoppala@linux.intel.com" target="_blank">mika.kuoppala@linux.intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/i915_reg.h | 3 ---<br>
drivers/gpu/drm/i915/intel_workarounds.c | 3 ---<br>
2 files changed, 6 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h<br>
index 7bdc214ffb6e..e0f5999fff07 100644<br>
--- a/drivers/gpu/drm/i915/i915_reg.h<br>
+++ b/drivers/gpu/drm/i915/i915_reg.h<br>
@@ -2859,9 +2859,6 @@ enum i915_power_well_id {<br>
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)<br>
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)<br>
<br>
-#define GEN10_CACHE_MODE_SS _MMIO(0xe420)<br>
-#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)<br>
-<br>
#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)<br>
#define GEN6_BLITTER_LOCK_SHIFT 16<br>
#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)<br>
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c<br>
index f8bb32e974f6..4bcdeaf8d98f 100644<br>
--- a/drivers/gpu/drm/i915/intel_workarounds.c<br>
+++ b/drivers/gpu/drm/i915/intel_workarounds.c<br>
@@ -508,9 +508,6 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)<br>
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,<br>
GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);<br>
<br>
- /* WaEnableFloatBlendOptimization:icl */<br>
- WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);<br>
-<br>
return 0;<br>
}<br>
<br>
-- <br>
2.17.1<br>
<br>
</blockquote></div></div>