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<b>Patch Details</b>
<table>
<tr><td><b>Series:</b></td><td>Begin enabling Xe_HP SDV and DG2 platforms</td></tr>
<tr><td><b>URL:</b></td><td><a href="https://patchwork.freedesktop.org/series/92135/">https://patchwork.freedesktop.org/series/92135/</a></td></tr>
<tr><td><b>State:</b></td><td>success</td></tr>
<tr><td><b>Details:</b></td><td><a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/index.html">https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/index.html</a></td></tr>
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<h1>CI Bug Log - changes from CI_DRM_10301 -> Patchwork_20518</h1>
<h2>Summary</h2>
<p><strong>SUCCESS</strong></p>
<p>No regressions found.</p>
<p>External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/index.html</p>
<h2>Known issues</h2>
<p>Here are the changes found in Patchwork_20518 that come from known issues:</p>
<h3>IGT changes</h3>
<h4>Issues hit</h4>
<ul>
<li>
<p>igt@amdgpu/amd_basic@query-info:</p>
<ul>
<li>fi-bsw-kefka: NOTRUN -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html">SKIP</a> (<a href="https://bugs.freedesktop.org/show_bug.cgi?id=109271">fdo#109271</a>) +17 similar issues</li>
</ul>
</li>
<li>
<p>igt@amdgpu/amd_basic@semaphore:</p>
<ul>
<li>fi-bsw-nick: NOTRUN -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html">SKIP</a> (<a href="https://bugs.freedesktop.org/show_bug.cgi?id=109271">fdo#109271</a>) +17 similar issues</li>
</ul>
</li>
<li>
<p>igt@gem_exec_suspend@basic-s0:</p>
<ul>
<li>fi-cfl-8109u: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10301/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0.html">INCOMPLETE</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/155">i915#155</a>)</li>
</ul>
</li>
</ul>
<h4>Possible fixes</h4>
<ul>
<li>
<p>igt@i915_selftest@live@execlists:</p>
<ul>
<li>
<p>fi-bsw-nick: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10301/fi-bsw-nick/igt@i915_selftest@live@execlists.html">INCOMPLETE</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/2782">i915#2782</a> / <a href="https://gitlab.freedesktop.org/drm/intel/issues/2940">i915#2940</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/fi-bsw-nick/igt@i915_selftest@live@execlists.html">PASS</a></p>
</li>
<li>
<p>fi-bsw-kefka: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10301/fi-bsw-kefka/igt@i915_selftest@live@execlists.html">INCOMPLETE</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/2782">i915#2782</a> / <a href="https://gitlab.freedesktop.org/drm/intel/issues/2940">i915#2940</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20518/fi-bsw-kefka/igt@i915_selftest@live@execlists.html">PASS</a></p>
</li>
</ul>
</li>
</ul>
<h2>Participating hosts (37 -> 33)</h2>
<p>Missing (4): fi-bdw-samus fi-bsw-cyan fi-cml-s fi-ilk-650 </p>
<h2>Build changes</h2>
<ul>
<li>Linux: CI_DRM_10301 -> Patchwork_20518</li>
</ul>
<p>CI-20190529: 20190529<br />
CI_DRM_10301: 3d3ff5917ce204b783f4847c14e8839fde358a3a @ git://anongit.freedesktop.org/gfx-ci/linux<br />
IGT_6128: b24e5949af7e51f0af484d2ce4cb4c5a41ac5358 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git<br />
Patchwork_20518: 133ddb5ea323de062e5fbe46bd3798f33ae0f437 @ git://anongit.freedesktop.org/gfx-ci/linux</p>
<p>== Linux commits ==</p>
<p>133ddb5ea323 drm/i915/dg2: Configure PCON in DP pre-enable path<br />
fde12e824f05 drm/i915/dg2: Update to bigjoiner path<br />
ba4968e55d28 drm/i915/display/dsc: Set BPP in the kernel<br />
edfb2d6e0ea6 drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable<br />
9e2db54a273c drm/i915/dg2: Add DG2 to the PSR2 defeature list<br />
6bbd5a823a50 drm/i915/dg2: Update lane disable power state during PSR<br />
3b3857d8d39d drm/i915/dg2: Wait for SNPS PHY calibration during display init<br />
3d1b5babd51e drm/i915/dg2: Classify DG2 PHY types<br />
c32649b18330 drm/i915/dg2: Update modeset sequences<br />
c6953118f038 drm/i915/dg2: Add vswing programming for SNPS phys<br />
53a063c8f301 drm/i915/dg2: Add MPLLB programming for HDMI<br />
c9166bb312a8 drm/i915/dg2: Add MPLLB programming for SNPS PHY<br />
9474127ed4be drm/i915/dg2: DG2 has fixed memory bandwidth<br />
ba19ca3a61d3 drm/i915/dg2: Don't read DRAM info<br />
0a348ed50a66 drm/i915/dg2: Don't program BW_BUDDY registers<br />
32e45599e864 drm/i915/dg2: Add dbuf programming<br />
4412055dac14 drm/i915/dg2: Setup display outputs<br />
98e804dd9e17 drm/i915/dg2: Don't wait for AUX power well enable ACKs<br />
97a61600ba6e drm/i915/dg2: Skip shared DPLL handling<br />
28764cd2c9ae drm/i915/dg2: Add cdclk table and reference clock<br />
2eecc2959819 drm/i915/dg2: Add fake PCH<br />
76612645f39d drm/i915/dg2: Define MOCS table for DG2<br />
4da0b4be71af drm/i915/dg2: Report INSTDONE_GEOM values in error state<br />
8f4f5f5be899 drm/i915/dg2: Maintain backward-compatible nested batch behavior<br />
b4672468008b drm/i915/dg2: Add new LRI reg offsets<br />
18222398e843 drm/i915/dg2: Add SQIDI steering<br />
361dc98d37a9 drm/i915/dg2: Update LNCF steering ranges<br />
85fa4b39b442 drm/i915/dg2: Add forcewake table<br />
3716a646ee5d drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV<br />
7841e2ad91bd drm/i915/dg2: add DG2 platform info<br />
694b8e11d8f3 drm/i915/xehpsdv: Read correct RP_STATE_CAP register<br />
01476822d53d drm/i915/xehpsdv: factor out function to read RP_STATE_CAP<br />
4aad6e79cab0 drm/i915/xehpsdv: Define MOCS table for XeHP SDV<br />
6b890b15a53c drm/i915/xehpsdv: Define steering tables<br />
e3ff7b0ad237 drm/i915/xehpsdv: Add compute DSS type<br />
39a55b65b031 drm/i915/xehpsdv: Add maximum sseu limits<br />
58cddebf678c drm/i915/xehp: Changes to ss/eu definitions<br />
717f4e93c77c drm/i915/xehpsdv: add initial XeHP SDV definitions<br />
b5f0a7fb4bd7 drm/i915/xehp: Loop over all gslices for INSTDONE processing<br />
fa143e9788fb drm/i915/xehp: handle new steering options<br />
c88fc01c6c90 drm/i915/xehp: New engine context offsets<br />
6ffc374c0e68 drm/i915/xehp: Handle new device context ID format<br />
20d2cc13bee1 drm/i915/xehp: Define multicast register ranges<br />
1172112c84c7 drm/i915/xehp: Xe_HP forcewake support<br />
16294d658a13 drm/i915/xehp: Extra media engines - Part 3 (reset)<br />
feeddd16cf72 drm/i915/xehp: Extra media engines - Part 2 (interrupts)<br />
d3e12edbacc3 drm/i915/xehp: Extra media engines - Part 1 (engine definitions)<br />
9d74c6dfe137 drm/i915/selftests: Allow for larger engine counts<br />
36e86d116247 drm/i915/gen12: Use fuse info to enable SFC<br />
f085b19fbe3a drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based<br />
be574a1b4ce4 drm/i915: Fork DG1 interrupt handler<br />
204773918d46 drm/i915: Add XE_HP initial definitions<br />
23da9848b630 drm/i915: Add "release id" version</p>
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