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Tested and confirmed working on TGL-H Dell platforms.</div>
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<div style="font-family:Tahoma; font-size:13px"><span style="font-size:12pt; font-family:Calibri,Helvetica,sans-serif">David Box</span><br>
<span style="font-size:12pt; font-family:Calibri,Helvetica,sans-serif">Linux Power Management
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<span style="font-size:12pt; font-family:Calibri,Helvetica,sans-serif">IAGS/SSE</span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Gupta, Anshuman <anshuman.gupta@intel.com><br>
<b>Sent:</b> Monday, July 12, 2021 12:09 AM<br>
<b>To:</b> intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Box, David E <david.e.box@intel.com>; Gupta, Anshuman <anshuman.gupta@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Deak, Imre <imre.deak@intel.com><br>
<b>Subject:</b> [REBASED v2] drm/i915: Tweaked Wa_14010685332 for all PCHs</font>
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<div class="PlainText">dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform<br>
despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix state.<br>
<br>
The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked<br>
Wa_14010685332 sequence for every PCH since PCH_CNP.<br>
<br>
v2:<br>
- removed RKL from comment and simplified condition. [Rodrigo]<br>
<br>
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms")<br>
Cc: Matt Roper <matthew.d.roper@intel.com><br>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com><br>
Cc: Imre Deak <imre.deak@intel.com><br>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com><br>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com><br>
---<br>
.../drm/i915/display/intel_display_power.c | 16 +++++++-------<br>
drivers/gpu/drm/i915/i915_irq.c | 21 -------------------<br>
2 files changed, 8 insertions(+), 29 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c<br>
index 285380079aab..28a363119560 100644<br>
--- a/drivers/gpu/drm/i915/display/intel_display_power.c<br>
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c<br>
@@ -6388,13 +6388,13 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915)<br>
if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||<br>
IS_BROXTON(i915)) {<br>
bxt_enable_dc9(i915);<br>
- /* Tweaked Wa_14010685332:icp,jsp,mcc */<br>
- if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)<br>
- intel_de_rmw(i915, SOUTH_CHICKEN1,<br>
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);<br>
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {<br>
hsw_enable_pc8(i915);<br>
}<br>
+<br>
+ /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */<br>
+ if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)<br>
+ intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);<br>
}<br>
<br>
void intel_display_power_resume_early(struct drm_i915_private *i915)<br>
@@ -6403,13 +6403,13 @@ void intel_display_power_resume_early(struct drm_i915_private *i915)<br>
IS_BROXTON(i915)) {<br>
gen9_sanitize_dc_state(i915);<br>
bxt_disable_dc9(i915);<br>
- /* Tweaked Wa_14010685332:icp,jsp,mcc */<br>
- if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)<br>
- intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);<br>
-<br>
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {<br>
hsw_disable_pc8(i915);<br>
}<br>
+<br>
+ /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */<br>
+ if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)<br>
+ intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);<br>
}<br>
<br>
void intel_display_power_suspend(struct drm_i915_private *i915)<br>
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c<br>
index 1d4c683c9de9..99c75a9d7ffa 100644<br>
--- a/drivers/gpu/drm/i915/i915_irq.c<br>
+++ b/drivers/gpu/drm/i915/i915_irq.c<br>
@@ -3064,24 +3064,6 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)<br>
spin_unlock_irq(&dev_priv->irq_lock);<br>
}<br>
<br>
-static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)<br>
-{<br>
- struct intel_uncore *uncore = &dev_priv->uncore;<br>
-<br>
- /*<br>
- * Wa_14010685332:cnp/cmp,tgp,adp<br>
- * TODO: Clarify which platforms this applies to<br>
- * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as<br>
- * on earlier platforms and whether the workaround is also needed for runtime suspend/resume<br>
- */<br>
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||<br>
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {<br>
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,<br>
- SBCLK_RUN_REFCLK_DIS);<br>
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);<br>
- }<br>
-}<br>
-<br>
static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)<br>
{<br>
struct intel_uncore *uncore = &dev_priv->uncore;<br>
@@ -3115,7 +3097,6 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)<br>
if (HAS_PCH_SPLIT(dev_priv))<br>
ibx_irq_reset(dev_priv);<br>
<br>
- cnp_display_clock_wa(dev_priv);<br>
}<br>
<br>
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)<br>
@@ -3159,8 +3140,6 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)<br>
<br>
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)<br>
GEN3_IRQ_RESET(uncore, SDE);<br>
-<br>
- cnp_display_clock_wa(dev_priv);<br>
}<br>
<br>
static void gen11_irq_reset(struct drm_i915_private *dev_priv)<br>
-- <br>
2.26.2<br>
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