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<b>Patch Details</b>
<table>
<tr><td><b>Series:</b></td><td>Begin enabling Xe_HP SDV and DG2 platforms (rev6)</td></tr>
<tr><td><b>URL:</b></td><td><a href="https://patchwork.freedesktop.org/series/92135/">https://patchwork.freedesktop.org/series/92135/</a></td></tr>
<tr><td><b>State:</b></td><td>success</td></tr>
<tr><td><b>Details:</b></td><td><a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/index.html">https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/index.html</a></td></tr>
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<h1>CI Bug Log - changes from CI_DRM_10382 -> Patchwork_20698</h1>
<h2>Summary</h2>
<p><strong>SUCCESS</strong></p>
<p>No regressions found.</p>
<p>External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/index.html</p>
<h2>Known issues</h2>
<p>Here are the changes found in Patchwork_20698 that come from known issues:</p>
<h3>IGT changes</h3>
<h4>Issues hit</h4>
<ul>
<li>
<p>igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:</p>
<ul>
<li>fi-tgl-1115g4: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10382/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/1887">i915#1887</a>)</li>
</ul>
</li>
<li>
<p>igt@runner@aborted:</p>
<ul>
<li>fi-tgl-1115g4: NOTRUN -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/fi-tgl-1115g4/igt@runner@aborted.html">FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/1602">i915#1602</a>)</li>
</ul>
</li>
</ul>
<h4>Possible fixes</h4>
<ul>
<li>igt@i915_selftest@live@hangcheck:<ul>
<li>{fi-hsw-gt1}: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10382/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/3303">i915#3303</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20698/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html">PASS</a></li>
</ul>
</li>
</ul>
<p>{name}: This element is suppressed. This means it is ignored when computing<br />
the status of the difference (SUCCESS, WARNING, or FAILURE).</p>
<h2>Participating hosts (43 -> 36)</h2>
<p>Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adls-4 fi-ctg-p8600 bat-adls-3 fi-bdw-samus </p>
<h2>Build changes</h2>
<ul>
<li>Linux: CI_DRM_10382 -> Patchwork_20698</li>
</ul>
<p>CI-20190529: 20190529<br />
CI_DRM_10382: 03db07ede8eeeae5fa12cb07684084e531db377b @ git://anongit.freedesktop.org/gfx-ci/linux<br />
IGT_6149: 34ff2cf2bc352dce691593db803389fe0eb2be03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git<br />
Patchwork_20698: bcdeb7e1edf0bcaf0131923ff8fec88d6da379d2 @ git://anongit.freedesktop.org/gfx-ci/linux</p>
<p>== Linux commits ==</p>
<p>bcdeb7e1edf0 drm/i915/dg2: Configure PCON in DP pre-enable path<br />
76199f2888ef drm/i915/dg2: Update to bigjoiner path<br />
aa3166a1e277 drm/i915/dg2: Update lane disable power state during PSR<br />
e45963bba93a drm/i915/dg2: Wait for SNPS PHY calibration during display init<br />
c17b50b62625 drm/i915/dg2: Update modeset sequences<br />
b1efd88312b8 drm/i915/dg2: Add vswing programming for SNPS phys<br />
ba80b83c84a9 drm/i915/dg2: Add MPLLB programming for HDMI<br />
2f1319f28f47 drm/i915/dg2: Add MPLLB programming for SNPS PHY<br />
a4f5ef996270 drm/i915/dg2: Define MOCS table for DG2<br />
6a189a7ddf4d drm/i915/dg2: Report INSTDONE_GEOM values in error state<br />
9542a06a5a35 drm/i915/dg2: Maintain backward-compatible nested batch behavior<br />
e1706eba9559 drm/i915/dg2: Add new LRI reg offsets<br />
f7b8d3a066bf drm/i915/dg2: Add SQIDI steering<br />
134cfcfd9c84 drm/i915/dg2: Update LNCF steering ranges<br />
1ace9a8d1b2a drm/i915/dg2: Add forcewake table<br />
4057f5104c28 drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV<br />
da9489e90eda drm/i915/xehpsdv: Read correct RP_STATE_CAP register<br />
83b0be478cb4 drm/i915/xehpsdv: factor out function to read RP_STATE_CAP<br />
3def48fb4238 drm/i915/xehpsdv: Define MOCS table for XeHP SDV<br />
0a73f890d107 drm/i915/xehpsdv: Define steering tables<br />
278d359e56da drm/i915/xehpsdv: Add compute DSS type<br />
94a690b2b730 drm/i915/xehpsdv: Add maximum sseu limits<br />
456e57370fcd drm/i915/xehp: Changes to ss/eu definitions<br />
21933a40845a drm/i915/xehp: Loop over all gslices for INSTDONE processing<br />
70b1a7998cf4 drm/i915/xehp: handle new steering options<br />
2b3f9bef9095 drm/i915/xehp: Xe_HP forcewake support<br />
25bc3daa002b drm/i915/xehp: Extra media engines - Part 3 (reset)<br />
3f65d319057d drm/i915/xehp: Extra media engines - Part 2 (interrupts)<br />
42a1f6157116 drm/i915/xehp: Extra media engines - Part 1 (engine definitions)<br />
f90c0193e566 drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP()</p>
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