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<p>Hi Robin,</p>
[ +arm64 maintainers for their awareness, which would have been a
good thing to do from the start ]
<ul>
<li>Thanks for adding the arm64 maintainer and sorry I didn't rope
them in sooner.</li>
</ul>
Why does i915 need to ensure the CPU's instruction cache is coherent
with its data cache? Is it a self-modifying driver?
<ul>
<li>Also thanks for pointing this out. Initially I was using
dcache_clean_inval_poc, which seem to be the equivalently to
what x86 is doing for dcache flushing, but it was giving me
build errors since its not on the global list of kernel symbols.
And after revisiting the documentation for
caches_clean_inval_pou, it won't fly for what we are trying to
do. Moving forward, what would you (or someone in the ARM
community) suggest we do? Could it be possible to export
dcache_clean_inval_poc as a global symbol?<br>
</li>
</ul>
On 2022-02-25 10:24 a.m., Robin Murphy wrote:<br>
<blockquote type="cite" cite="mid:5c254623-98d2-75f3-52cb-209b8de304b6@arm.com">[ +arm64
maintainers for their awareness, which would have been a good
thing to do from the start ]
<br>
<br>
On 2022-02-25 03:24, Michael Cheng wrote:
<br>
<blockquote type="cite">Add arm64 support for
drm_clflush_virt_range. caches_clean_inval_pou
<br>
performs a flush by first performing a clean, follow by an
invalidation
<br>
operation.
<br>
<br>
v2 (Michael Cheng): Use correct macro for cleaning and
invalidation the
<br>
dcache. Thanks Tvrtko for the suggestion.
<br>
<br>
v3 (Michael Cheng): Replace asm/cacheflush.h with
linux/cacheflush.h
<br>
<br>
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc
as a
<br>
symbol that could be use by other modules, thus use
<br>
caches_clean_inval_pou instead. Also this version
<br>
removes include for cacheflush, since its
already
<br>
included base on architecture type.
<br>
<br>
Signed-off-by: Michael Cheng <a class="moz-txt-link-rfc2396E" href="mailto:michael.cheng@intel.com"><michael.cheng@intel.com></a>
<br>
Reviewed-by: Matt Roper <a class="moz-txt-link-rfc2396E" href="mailto:matthew.d.roper@intel.com"><matthew.d.roper@intel.com></a>
<br>
---
<br>
drivers/gpu/drm/drm_cache.c | 5 +++++
<br>
1 file changed, 5 insertions(+)
<br>
<br>
diff --git a/drivers/gpu/drm/drm_cache.c
b/drivers/gpu/drm/drm_cache.c
<br>
index c3e6e615bf09..81c28714f930 100644
<br>
--- a/drivers/gpu/drm/drm_cache.c
<br>
+++ b/drivers/gpu/drm/drm_cache.c
<br>
@@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned
long length)
<br>
if (wbinvd_on_all_cpus())
<br>
pr_err("Timed out waiting for cache flush\n");
<br>
+
<br>
+#elif defined(CONFIG_ARM64)
<br>
+ void *end = addr + length;
<br>
+ caches_clean_inval_pou((unsigned long)addr, (unsigned
long)end);
<br>
</blockquote>
<br>
Why does i915 need to ensure the CPU's instruction cache is
coherent with its data cache? Is it a self-modifying driver?
<br>
<br>
Robin.
<br>
<br>
(Note that the above is somewhat of a loaded question, and I do
actually have half an idea of what you're trying to do here and
why it won't fly, but I'd like to at least assume you've read the
documentation of the function you decided was OK to use)
<br>
<br>
<blockquote type="cite">+
<br>
#else
<br>
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
<br>
#endif
<br>
</blockquote>
</blockquote>
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