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<div>On Fri, 2023-01-06 at 19:33 +0000, Sripada, Radhakrishna wrote:</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>Pushed with the nit's fixed. Thanks for the patch and review.<br>
</div>
</blockquote>
<div><br>
</div>
<div>Next time please modify, resend and wait the BAT. We had</div>
<div>seen cases in the past where the modification ended in a bad code</div>
<div>that broken compilation and everyone else.</div>
<div><br>
</div>
<div>Small modifications while merging are only acceptable in the commit</div>
<div>messages.</div>
<div><br>
</div>
<div>Thanks,</div>
<div>Rodrigo.</div>
<div><br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div>- Radhakrishna(RK) Sripada<br>
</div>
<div><br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>-----Original Message-----<br>
</div>
<div>From: Intel-gfx <<a href="mailto:intel-gfx-bounces@lists.freedesktop.org">intel-gfx-bounces@lists.freedesktop.org</a>> On Behalf Of Rodrigo<br>
</div>
<div>Vivi<br>
</div>
<div>Sent: Friday, January 6, 2023 5:04 AM<br>
</div>
<div>To: Atwood, Matthew S <<a href="mailto:matthew.s.atwood@intel.com">matthew.s.atwood@intel.com</a>><br>
</div>
<div>Cc: <a href="mailto:intel-gfx@lists.freedesktop.org">intel-gfx@lists.freedesktop.org</a>; De Marchi, Lucas<br>
</div>
<div><<a href="mailto:lucas.demarchi@intel.com">lucas.demarchi@intel.com</a>><br>
</div>
<div>Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add initial gt workarounds<br>
</div>
<div><br>
</div>
<div>On Thu, Jan 05, 2023 at 03:44:08PM -0800, Matt Atwood wrote:<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>From: Matt Roper <<a href="mailto:matthew.d.roper@intel.com">matthew.d.roper@intel.com</a>><br>
</div>
<div><br>
</div>
<div>This patch introduces initial gt workarounds for the MTL platform.<br>
</div>
<div><br>
</div>
<div>v2: drop redundant/stale comments specifying wa platforms affected<br>
</div>
<div>(Lucas).<br>
</div>
<div>v3: drop additional redundant stale comments (MattR)<br>
</div>
<div><br>
</div>
<div>Bspec: 66622<br>
</div>
<div><br>
</div>
<div>Signed-off-by: Matt Roper <<a href="mailto:matthew.d.roper@intel.com">matthew.d.roper@intel.com</a>><br>
</div>
<div>Signed-off-by: Matt Atwood <<a href="mailto:matthew.s.atwood@intel.com">matthew.s.atwood@intel.com</a>><br>
</div>
<div>---<br>
</div>
<div> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-<br>
</div>
<div> .../drm/i915/gt/intel_execlists_submission.c | 6 +-<br>
</div>
<div> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 11 +-<br>
</div>
<div> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +<br>
</div>
<div> drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +++++++++++++-----<br>
</div>
<div> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +-<br>
</div>
<div> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-<br>
</div>
<div> drivers/gpu/drm/i915/i915_drv.h | 4 +<br>
</div>
<div> drivers/gpu/drm/i915/intel_device_info.c | 6 +<br>
</div>
<div> 9 files changed, 128 insertions(+), 42 deletions(-)<br>
</div>
<div><br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/gt/intel_engine_cs.c<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index 99c4b866addd..e3f30bdf7e61 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c<br>
</div>
<div>@@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine,<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> intel_uncore_write_fw(uncore, mode,<br>
</div>
</blockquote>
<div>_MASKED_BIT_ENABLE(STOP_RING));<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div> /*<br>
</div>
<div>- * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is<br>
</div>
<div>+ * Wa_22011802037 : Prior to doing a reset, ensure CS is<br>
</div>
</blockquote>
<div><br>
</div>
<div> ^ you could've had also removed the extra space<br>
</div>
<div><br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> * stopped, set ring stop bit and prefetch disable bit to halt CS<br>
</div>
<div> */<br>
</div>
<div>- if (IS_GRAPHICS_VER(engine->i915, 11, 12))<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ (GRAPHICS_VER(engine->i915) >= 11 &&<br>
</div>
<div>+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))<br>
</div>
</blockquote>
<div><br>
</div>
<div>this is getting hard to read, but yeap, this is the only way...<br>
</div>
<div><br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-<br>
</div>
<div>mmio_base),<br>
</div>
<div><br>
</div>
</blockquote>
<div>_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index 2daffa7c7dfd..18ffe55282e5 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c<br>
</div>
<div>@@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> intel_engine_stop_cs(engine);<br>
</div>
<div><br>
</div>
<div> /*<br>
</div>
<div>- * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we<br>
</div>
</blockquote>
<div>need<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ * Wa_22011802037: In addition to stopping the cs, we need<br>
</div>
<div> * to wait for any pending mi force wakeups<br>
</div>
<div> */<br>
</div>
<div>- if (IS_GRAPHICS_VER(engine->i915, 11, 12))<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ (GRAPHICS_VER(engine->i915) >= 11 &&<br>
</div>
<div>+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))<br>
</div>
<div> intel_engine_wait_for_pending_mi_fw(engine);<br>
</div>
<div><br>
</div>
<div> engine->execlists.reset_ccid = active_ccid(engine);<br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index 41a237509dcf..4127830c33ca 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c<br>
</div>
<div>@@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)<br>
</div>
<div> if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {<br>
</div>
<div> gt->steering_table[OADDRM] =<br>
</div>
</blockquote>
<div>xelpmp_oaddrm_steering_table;<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {<br>
</div>
<div>- fuse = REG_FIELD_GET(GT_L3_EXC_MASK,<br>
</div>
<div>- intel_uncore_read(gt->uncore,<br>
</div>
</blockquote>
<div>XEHP_FUSE4));<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ /* Wa_14016747170 */<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))<br>
</div>
<div>+ fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,<br>
</div>
<div>+ intel_uncore_read(gt->uncore,<br>
</div>
<div>+<br>
</div>
</blockquote>
<div>MTL_GT_ACTIVITY_FACTOR));<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ else<br>
</div>
<div>+ fuse = REG_FIELD_GET(GT_L3_EXC_MASK,<br>
</div>
<div>+ intel_uncore_read(gt->uncore,<br>
</div>
</blockquote>
<div>XEHP_FUSE4));<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div> /*<br>
</div>
<div> * Despite the register field being named "exclude mask" the<br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index f8eb807b56f9..8ad084bd35d5 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br>
</div>
<div>@@ -414,6 +414,7 @@<br>
</div>
<div> #define TBIMR_FAST_CLIP REG_BIT(5)<br>
</div>
<div><br>
</div>
<div> #define VFLSKPD MCR_REG(0x62a8)<br>
</div>
<div>+#define VF_PREFETCH_TLB_DIS REG_BIT(5)<br>
</div>
<div> #define DIS_OVER_FETCH_CACHE REG_BIT(1)<br>
</div>
<div> #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)<br>
</div>
<div><br>
</div>
<div>@@ -1535,6 +1536,10 @@<br>
</div>
<div><br>
</div>
<div> #define MTL_MEDIA_MC6 _MMIO(0x138048)<br>
</div>
<div><br>
</div>
<div>+/* Wa_14016747170 */<br>
</div>
</blockquote>
<div><br>
</div>
<div>no need for the wa identifier in here.<br>
</div>
<div><br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+#define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)<br>
</div>
<div>+#define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3)<br>
</div>
<div>+<br>
</div>
<div> #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)<br>
</div>
<div> #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7<br>
</div>
<div><br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/gt/intel_workarounds.c<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index bf84efb3f15f..002ba7c2b1ed 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c<br>
</div>
<div>@@ -786,6 +786,32 @@ static void dg2_ctx_workarounds_init(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine,<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> wa_masked_en(wal, CACHE_MODE_1,<br>
</div>
</blockquote>
<div>MSAA_OPTIMIZATION_REDUC_DISABLE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> }<br>
</div>
<div><br>
</div>
<div>+static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,<br>
</div>
<div>+ struct i915_wa_list *wal)<br>
</div>
<div>+{<br>
</div>
<div>+ struct drm_i915_private *i915 = engine->i915;<br>
</div>
<div>+<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {<br>
</div>
<div>+ /* Wa_14014947963 */<br>
</div>
<div>+ wa_masked_field_set(wal, VF_PREEMPTION,<br>
</div>
<div>+ PREEMPTION_VERTEX_COUNT, 0x4000);<br>
</div>
<div>+<br>
</div>
<div>+ /* Wa_16013271637 */<br>
</div>
<div>+ wa_mcr_masked_en(wal,<br>
</div>
</blockquote>
<div>XEHP_SLICE_COMMON_ECO_CHICKEN1,<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ MSC_MSAA_REODER_BUF_BYPASS_DISABLE);<br>
</div>
<div>+<br>
</div>
<div>+ /* Wa_18019627453 */<br>
</div>
<div>+ wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);<br>
</div>
<div>+<br>
</div>
<div>+ /* Wa_18018764978 */<br>
</div>
<div>+ wa_masked_en(wal, PSS_MODE2,<br>
</div>
</blockquote>
<div>SCOREBOARD_STALL_FLUSH_CONTROL);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ }<br>
</div>
<div>+<br>
</div>
<div>+ /* Wa_18019271663 */<br>
</div>
<div>+ wa_masked_en(wal, CACHE_MODE_1,<br>
</div>
</blockquote>
<div>MSAA_OPTIMIZATION_REDUC_DISABLE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+}<br>
</div>
<div>+<br>
</div>
<div> static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,<br>
</div>
<div> struct i915_wa_list *wal)<br>
</div>
<div> {<br>
</div>
<div>@@ -872,7 +898,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs<br>
</div>
</blockquote>
<div>*engine,<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> if (engine->class != RENDER_CLASS)<br>
</div>
<div> goto done;<br>
</div>
<div><br>
</div>
<div>- if (IS_PONTEVECCHIO(i915))<br>
</div>
<div>+ if (IS_METEORLAKE(i915))<br>
</div>
<div>+ mtl_ctx_workarounds_init(engine, wal);<br>
</div>
<div>+ else if (IS_PONTEVECCHIO(i915))<br>
</div>
<div> ; /* noop; none at this time */<br>
</div>
<div> else if (IS_DG2(i915))<br>
</div>
<div> dg2_ctx_workarounds_init(engine, wal);<br>
</div>
<div>@@ -1628,7 +1656,10 @@ pvc_gt_workarounds_init(struct intel_gt *gt,<br>
</div>
</blockquote>
<div>struct i915_wa_list *wal)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> static void<br>
</div>
<div> xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)<br>
</div>
<div> {<br>
</div>
<div>- /* FIXME: Actual workarounds will be added in future patch(es) */<br>
</div>
<div>+ /* Wa_14014830051 */<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))<br>
</div>
<div>+ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);<br>
</div>
<div><br>
</div>
<div> /*<br>
</div>
<div> * Unlike older platforms, we no longer setup implicit steering here;<br>
</div>
<div>@@ -2168,7 +2199,9 @@ void intel_engine_init_whitelist(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div> wa_init_start(w, engine->gt, "whitelist", engine->name);<br>
</div>
<div><br>
</div>
<div>- if (IS_PONTEVECCHIO(i915))<br>
</div>
<div>+ if (IS_METEORLAKE(i915))<br>
</div>
<div>+ ; /* noop; none at this time */<br>
</div>
<div>+ else if (IS_PONTEVECCHIO(i915))<br>
</div>
<div> pvc_whitelist_build(engine);<br>
</div>
<div> else if (IS_DG2(i915))<br>
</div>
<div> dg2_whitelist_build(engine);<br>
</div>
<div>@@ -2278,6 +2311,34 @@ rcs_engine_wa_init(struct intel_engine_cs<br>
</div>
</blockquote>
<div>*engine, struct i915_wa_list *wal)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> {<br>
</div>
<div> struct drm_i915_private *i915 = engine->i915;<br>
</div>
<div><br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {<br>
</div>
<div>+ /* Wa_22014600077 */<br>
</div>
<div>+ wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,<br>
</div>
<div>+ ENABLE_EU_COUNT_FOR_TDL_FLUSH);<br>
</div>
<div>+ }<br>
</div>
<div>+<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||<br>
</div>
<div>+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {<br>
</div>
<div>+ /* Wa_1509727124 */<br>
</div>
<div>+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,<br>
</div>
<div>+ SC_DISABLE_POWER_OPTIMIZATION_EBB);<br>
</div>
<div>+<br>
</div>
<div>+ /* Wa_22013037850 */<br>
</div>
<div>+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,<br>
</div>
<div>+ DISABLE_128B_EVICTION_COMMAND_UDW);<br>
</div>
<div>+ }<br>
</div>
<div>+<br>
</div>
<div>+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||<br>
</div>
<div>+ IS_DG2_G11(i915) || IS_DG2_G12(i915) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {<br>
</div>
<div>+ /* Wa_22012856258 */<br>
</div>
<div>+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,<br>
</div>
<div>+ GEN12_DISABLE_READ_SUPPRESSION);<br>
</div>
<div>+ }<br>
</div>
<div>+<br>
</div>
<div> if (IS_DG2(i915)) {<br>
</div>
<div> /* Wa_1509235366:dg2 */<br>
</div>
<div> wa_write_or(wal, GEN12_GAMCNTRL_CTRL,<br>
</div>
</blockquote>
<div>INVALIDATION_BROADCAST_MODE_DIS |<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>@@ -2289,13 +2350,6 @@ rcs_engine_wa_init(struct intel_engine_cs<br>
</div>
</blockquote>
<div>*engine, struct i915_wa_list *wal)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,<br>
</div>
</blockquote>
<div>GEN12_ENABLE_LARGE_GRF_MODE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> }<br>
</div>
<div><br>
</div>
<div>- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||<br>
</div>
<div>- IS_DG2_G11(i915) || IS_DG2_G12(i915)) {<br>
</div>
<div>- /* Wa_1509727124:dg2 */<br>
</div>
<div>- wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,<br>
</div>
<div>- SC_DISABLE_POWER_OPTIMIZATION_EBB);<br>
</div>
<div>- }<br>
</div>
<div>-<br>
</div>
<div> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||<br>
</div>
<div> IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {<br>
</div>
<div> /* Wa_14012419201:dg2 */<br>
</div>
<div>@@ -2327,14 +2381,6 @@ rcs_engine_wa_init(struct intel_engine_cs<br>
</div>
</blockquote>
<div>*engine, struct i915_wa_list *wal)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||<br>
</div>
<div> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {<br>
</div>
<div>- /* Wa_22013037850:dg2 */<br>
</div>
<div>- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,<br>
</div>
<div>- DISABLE_128B_EVICTION_COMMAND_UDW);<br>
</div>
<div>-<br>
</div>
<div>- /* Wa_22012856258:dg2 */<br>
</div>
<div>- wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,<br>
</div>
<div>- GEN12_DISABLE_READ_SUPPRESSION);<br>
</div>
<div>-<br>
</div>
<div> /*<br>
</div>
<div> * Wa_22010960976:dg2<br>
</div>
<div> * Wa_14013347512:dg2<br>
</div>
<div>@@ -2944,6 +2990,27 @@ general_render_compute_wa_init(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine, struct i915_wa_li<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div> add_render_compute_tuning_settings(i915, wal);<br>
</div>
<div><br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_PONTEVECCHIO(i915) ||<br>
</div>
<div>+ IS_DG2(i915)) {<br>
</div>
<div>+ /* Wa_18018781329 */<br>
</div>
<div>+ wa_mcr_write_or(wal, RENDER_MOD_CTRL,<br>
</div>
</blockquote>
<div>FORCE_MISS_FTLB);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);<br>
</div>
<div>+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);<br>
</div>
<div>+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);<br>
</div>
<div>+<br>
</div>
<div>+ /* Wa_22014226127 */<br>
</div>
<div>+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,<br>
</div>
</blockquote>
<div>DISABLE_D8_D16_COASLESCE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ }<br>
</div>
<div>+<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_DG2(i915)) {<br>
</div>
<div>+ /* Wa_18017747507 */<br>
</div>
<div>+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,<br>
</div>
</blockquote>
<div>POLYGON_TRIFAN_LINELOOP_DISABLE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ }<br>
</div>
<div>+<br>
</div>
<div> if (IS_PONTEVECCHIO(i915)) {<br>
</div>
<div> /* Wa_16016694945 */<br>
</div>
<div> wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0,<br>
</div>
</blockquote>
<div>XEHPC_OVRLSCCC);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>@@ -2985,17 +3052,8 @@ general_render_compute_wa_init(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine, struct i915_wa_li<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> /* Wa_14015227452:dg2,pvc */<br>
</div>
<div> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4,<br>
</div>
</blockquote>
<div>XEHP_DIS_BBL_SYSPIPE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div>- /* Wa_22014226127:dg2,pvc */<br>
</div>
<div>- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,<br>
</div>
</blockquote>
<div>DISABLE_D8_D16_COASLESCE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>-<br>
</div>
<div> /* Wa_16015675438:dg2,pvc */<br>
</div>
<div> wa_masked_en(wal, FF_SLICE_CS_CHICKEN2,<br>
</div>
</blockquote>
<div>GEN12_PERF_FIX_BALANCING_CFE_DISABLE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>-<br>
</div>
<div>- /* Wa_18018781329:dg2,pvc */<br>
</div>
<div>- wa_mcr_write_or(wal, RENDER_MOD_CTRL,<br>
</div>
</blockquote>
<div>FORCE_MISS_FTLB);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>- wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);<br>
</div>
<div>- wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);<br>
</div>
<div>- wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);<br>
</div>
<div> }<br>
</div>
<div><br>
</div>
<div> if (IS_DG2(i915)) {<br>
</div>
<div>@@ -3004,9 +3062,6 @@ general_render_compute_wa_init(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine, struct i915_wa_li<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> * Wa_22015475538:dg2<br>
</div>
<div> */<br>
</div>
<div> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,<br>
</div>
</blockquote>
<div>DIS_CHAIN_2XSIMD8);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>-<br>
</div>
<div>- /* Wa_18017747507:dg2 */<br>
</div>
<div>- wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,<br>
</div>
</blockquote>
<div>POLYGON_TRIFAN_LINELOOP_DISABLE);<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> }<br>
</div>
<div><br>
</div>
<div> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) ||<br>
</div>
</blockquote>
<div>IS_DG2_G11(i915))<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/gt/uc/intel_guc.c<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index c0b5aa6fde26..1bccc175f9e6 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c<br>
</div>
<div>@@ -274,8 +274,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)<br>
</div>
<div> if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))<br>
</div>
<div> flags |= GUC_WA_GAM_CREDITS;<br>
</div>
<div><br>
</div>
<div>- /* Wa_14014475959:dg2 */<br>
</div>
<div>- if (IS_DG2(gt->i915))<br>
</div>
<div>+ /* Wa_14014475959 */<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ IS_DG2(gt->i915))<br>
</div>
<div> flags |= GUC_WA_HOLD_CCS_SWITCHOUT;<br>
</div>
<div><br>
</div>
<div> /*<br>
</div>
<div>@@ -289,7 +290,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)<br>
</div>
<div> flags |= GUC_WA_DUAL_QUEUE;<br>
</div>
<div><br>
</div>
<div> /* Wa_22011802037: graphics version 11/12 */<br>
</div>
<div>- if (IS_GRAPHICS_VER(gt->i915, 11, 12))<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||<br>
</div>
<div>+ (GRAPHICS_VER(gt->i915) >= 11 &&<br>
</div>
<div>+ GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))<br>
</div>
<div> flags |= GUC_WA_PRE_PARSER;<br>
</div>
<div><br>
</div>
<div> /* Wa_16011777198:dg2 */<br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index fe06c93cf6e3..b436dd7f12e4 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c<br>
</div>
<div>@@ -1621,7 +1621,7 @@ static void guc_engine_reset_prepare(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> intel_engine_stop_cs(engine);<br>
</div>
<div><br>
</div>
<div> /*<br>
</div>
<div>- * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we<br>
</div>
</blockquote>
<div>need<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ * Wa_22011802037: In addition to stopping the cs, we need<br>
</div>
<div> * to wait for any pending mi force wakeups<br>
</div>
<div> */<br>
</div>
<div> intel_engine_wait_for_pending_mi_fw(engine);<br>
</div>
<div>@@ -4203,8 +4203,10 @@ static void guc_default_vfuncs(struct<br>
</div>
</blockquote>
<div>intel_engine_cs *engine)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> engine->flags |= I915_ENGINE_HAS_TIMESLICES;<br>
</div>
<div><br>
</div>
<div> /* Wa_14014475959:dg2 */<br>
</div>
<div>- if (IS_DG2(engine->i915) && engine->class == COMPUTE_CLASS)<br>
</div>
<div>- engine->flags |=<br>
</div>
</blockquote>
<div>I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ if (engine->class == COMPUTE_CLASS)<br>
</div>
<div>+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,<br>
</div>
</blockquote>
<div>STEP_B0) ||<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ IS_DG2(engine->i915))<br>
</div>
<div>+ engine->flags |=<br>
</div>
</blockquote>
<div>I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div> /*<br>
</div>
<div> * TODO: GuC supports timeslicing and semaphores as well, but they're<br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/i915_drv.h<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/i915_drv.h<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index 48fd82722f12..f742328c4d95 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/i915_drv.h<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/i915_drv.h<br>
</div>
<div>@@ -735,6 +735,10 @@ IS_SUBPLATFORM(const struct drm_i915_private<br>
</div>
</blockquote>
<div>*i915,<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> (IS_METEORLAKE(__i915) && \<br>
</div>
<div> IS_DISPLAY_STEP(__i915, since, until))<br>
</div>
<div><br>
</div>
<div>+#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \<br>
</div>
<div>+ (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,<br>
</div>
</blockquote>
<div>INTEL_SUBPLATFORM_##variant) && \<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>+ IS_GRAPHICS_STEP(__i915, since, until))<br>
</div>
<div>+<br>
</div>
<div> /*<br>
</div>
<div> * DG2 hardware steppings are a bit unusual. The hardware design was forked<br>
</div>
</blockquote>
<div>to<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div> * create three variants (G10, G11, and G12) which each have distinct<br>
</div>
<div>diff --git a/drivers/gpu/drm/i915/intel_device_info.c<br>
</div>
</blockquote>
<div>b/drivers/gpu/drm/i915/intel_device_info.c<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div>index 849baf6c3b3c..05e90d09b208 100644<br>
</div>
<div>--- a/drivers/gpu/drm/i915/intel_device_info.c<br>
</div>
<div>+++ b/drivers/gpu/drm/i915/intel_device_info.c<br>
</div>
<div>@@ -343,6 +343,12 @@ static void intel_ipver_early_init(struct<br>
</div>
</blockquote>
<div>drm_i915_private *i915)<br>
</div>
<blockquote type="cite" style="margin:0 0 0 .8ex; border-left:2px #729fcf solid;padding-left:1ex">
<div><br>
</div>
<div> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),<br>
</div>
<div> &runtime->graphics.ip);<br>
</div>
<div>+ /* Wa_22012778468 */<br>
</div>
<div>+ if (runtime->graphics.ip.ver == 0x0 &&<br>
</div>
<div>+ INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {<br>
</div>
<div>+ RUNTIME_INFO(i915)->graphics.ip.ver = 12;<br>
</div>
<div>+ RUNTIME_INFO(i915)->graphics.ip.rel = 70;<br>
</div>
<div>+ }<br>
</div>
<div> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),<br>
</div>
<div> &runtime->display.ip);<br>
</div>
<div> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),<br>
</div>
<div>--<br>
</div>
<div>2.38.1<br>
</div>
<div><br>
</div>
</blockquote>
<div><br>
</div>
<div>with the extra space and the comments removed:<br>
</div>
<div><br>
</div>
<div>Reviewed-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com">rodrigo.vivi@intel.com</a>><br>
</div>
</blockquote>
</blockquote>
<div><br>
</div>
<div><span></span></div>
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