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> On 4/1/2023 8:38 AM, fei.yang@intel.com wrote:
<div class="ContentPasted0">>> From: Fei Yang <fei.yang@intel.com></div>
<div class="ContentPasted0">>></div>
<div class="ContentPasted0">>> On MTL, GT can no longer allocate on LLC - only the CPU can.</div>
<div class="ContentPasted0">>> This, along with addition of support for ADM/L4 cache calls a</div>
<div class="ContentPasted0">>> MOCS/PAT table update.</div>
<div class="ContentPasted0">>> Also add PTE encode functions for MTL as it has different PAT</div>
<div class="ContentPasted0">>> index definition than previous platforms.</div>
<div class="ContentPasted0">>></div>
<div class="ContentPasted0">>> BSpec: 44509, 45101, 44235</div>
<div class="ContentPasted0">>></div>
<div class="ContentPasted0">>> Cc: Matt Roper <matthew.d.roper@intel.com></div>
<div class="ContentPasted0">>> Cc: Lucas De Marchi <lucas.demarchi@intel.com></div>
<div class="ContentPasted0">>> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com></div>
<div class="ContentPasted0">>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com></div>
<div class="ContentPasted0">>> Signed-off-by: Fei Yang <fei.yang@intel.com></div>
<div class="ContentPasted0">>> ---</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 43 ++++++++++++--</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 3 +</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 ++++++++++-</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/gt/intel_gtt.c | 23 ++++++-</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/gt/intel_gtt.h | 20 ++++++-</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/gt/intel_mocs.c | 76 ++++++++++++++++++++++--</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-</div>
<div class="ContentPasted0">>> drivers/gpu/drm/i915/i915_pci.c | 1 +</div>
<div class="ContentPasted0">>> 9 files changed, 189 insertions(+), 17 deletions(-)</div>
<div class="ContentPasted0">>></div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c</div>
<div class="ContentPasted0">>> index b8027392144d..c5eacfdba1a5 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/display/intel_dpt.c</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c</div>
<div class="ContentPasted0">>> @@ -300,7 +300,7 @@ intel_dpt_create(struct intel_framebuffer *fb)</div>
<div class="ContentPasted0">>> vm->vma_ops.bind_vma = dpt_bind_vma;</div>
<div class="ContentPasted0">>> vm->vma_ops.unbind_vma = dpt_unbind_vma;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> - vm->pte_encode = gen8_ggtt_pte_encode;</div>
<div class="ContentPasted0">>> + vm->pte_encode = vm->gt->ggtt->vm.pte_encode;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> dpt->obj = dpt_obj;</div>
<div class="ContentPasted0">>> dpt->obj->is_dpt = true;</div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c</div>
<div class="ContentPasted0">>> index 4daaa6f55668..4197b43150cc 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c</div>
<div class="ContentPasted0">>> @@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,</div>
<div class="ContentPasted0">>> return pte;</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +static u64 mtl_pte_encode(dma_addr_t addr,</div>
<div class="ContentPasted0">>> + enum i915_cache_level level,</div>
<div class="ContentPasted0">>> + u32 flags)</div>
<div class="ContentPasted0">>> +{</div>
<div class="ContentPasted0">>> + gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + if (unlikely(flags & PTE_READ_ONLY))</div>
<div class="ContentPasted0">>> + pte &= ~GEN8_PAGE_RW;</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + if (flags & PTE_LM)</div>
<div class="ContentPasted0">>> + pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + switch (level) {</div>
<div class="ContentPasted0">>> + case I915_CACHE_NONE:</div>
<div class="ContentPasted0">>> + pte |= GEN12_PPGTT_PTE_PAT1;</div>
<div class="ContentPasted0">>> + break;</div>
<div class="ContentPasted0">>> + case I915_CACHE_LLC:</div>
<div class="ContentPasted0">>> + case I915_CACHE_L3_LLC:</div>
<div class="ContentPasted0">>> + pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;</div>
<div class="ContentPasted0">>> + break;</div>
<div class="ContentPasted0">>> + case I915_CACHE_WT:</div>
<div class="ContentPasted0">>> + pte |= GEN12_PPGTT_PTE_PAT0;</div>
<div class="ContentPasted0">>> + break;</div>
<div class="ContentPasted0">>> + }</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + return pte;</div>
<div class="ContentPasted0">>> +}</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)</div>
<div class="ContentPasted0">>> {</div>
<div class="ContentPasted0">>> struct drm_i915_private *i915 = ppgtt->vm.i915;</div>
<div class="ContentPasted0">>> @@ -427,7 +455,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,</div>
<div class="ContentPasted0">>> u32 flags)</div>
<div class="ContentPasted0">>> {</div>
<div class="ContentPasted0">>> struct i915_page_directory *pd;</div>
<div class="ContentPasted0">>> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);</div>
<div class="ContentPasted0">>> + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level, flags);</div>
<div class="ContentPasted0">>> gen8_pte_t *vaddr;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));</div>
<div class="ContentPasted0">>> @@ -580,7 +608,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,</div>
<div class="ContentPasted0">>> enum i915_cache_level cache_level,</div>
<div class="ContentPasted0">>> u32 flags)</div>
<div class="ContentPasted0">>> {</div>
<div class="ContentPasted0">>> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);</div>
<div class="ContentPasted0">>> + const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);</div>
<div class="ContentPasted0">>> unsigned int rem = sg_dma_len(iter->sg);</div>
<div class="ContentPasted0">>> u64 start = vma_res->start;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> @@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,</div>
<div class="ContentPasted0">>> GEM_BUG_ON(pt->is_compact);</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> vaddr = px_vaddr(pt);</div>
<div class="ContentPasted0">>> - vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);</div>
<div class="ContentPasted0">>> + vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);</div>
<div class="ContentPasted0">>> drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> @@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> vaddr = px_vaddr(pt);</div>
<div class="ContentPasted0">>> - vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);</div>
<div class="ContentPasted0">>> + vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level, flags);</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,</div>
<div class="ContentPasted0">>> @@ -820,7 +848,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)</div>
<div class="ContentPasted0">>> pte_flags |= PTE_LM;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> vm->scratch[0]->encode =</div>
<div class="ContentPasted0">>> - gen8_pte_encode(px_dma(vm->scratch[0]),</div>
<div class="ContentPasted0">>> + vm->pte_encode(px_dma(vm->scratch[0]),</div>
<div class="ContentPasted0">>> I915_CACHE_NONE, pte_flags);</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> for (i = 1; i <= vm->top; i++) {</div>
<div class="ContentPasted0">>> @@ -963,7 +991,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,</div>
<div class="ContentPasted0">>> */</div>
<div class="ContentPasted0">>> ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> - ppgtt->vm.pte_encode = gen8_pte_encode;</div>
<div class="ContentPasted0">>> + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))</div>
<div class="ContentPasted0">>> + ppgtt->vm.pte_encode = mtl_pte_encode;</div>
<div class="ContentPasted0">>> + else</div>
<div class="ContentPasted0">>> + ppgtt->vm.pte_encode = gen8_pte_encode;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;</div>
<div class="ContentPasted0">>> ppgtt->vm.insert_entries = gen8_ppgtt_insert;</div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h</div>
<div class="ContentPasted0">>> index f541d19264b4..6b8ce7f4d25a 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h</div>
<div class="ContentPasted0">>> @@ -18,5 +18,8 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,</div>
<div class="ContentPasted0">>> u64 gen8_ggtt_pte_encode(dma_addr_t addr,</div>
<div class="ContentPasted0">>> enum i915_cache_level level,</div>
<div class="ContentPasted0">>> u32 flags);</div>
<div class="ContentPasted0">>> +u64 mtl_ggtt_pte_encode(dma_addr_t addr,</div>
<div class="ContentPasted0">>> + unsigned int pat_index,</div>
<div class="ContentPasted0">>> + u32 flags);</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> #endif</div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c</div>
<div class="ContentPasted0">>> index 3c7f1ed92f5b..ba3109338aee 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c</div>
<div class="ContentPasted0">>> @@ -220,6 +220,33 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +u64 mtl_ggtt_pte_encode(dma_addr_t addr,</div>
<div class="ContentPasted0">>> + enum i915_cache_level level,</div>
<div class="ContentPasted0">>> + u32 flags)</div>
<div class="ContentPasted0">>> +{</div>
<div class="ContentPasted0">>> + gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + GEM_BUG_ON(addr & ~GEN12_GGTT_PTE_ADDR_MASK);</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + if (flags & PTE_LM)</div>
<div class="ContentPasted0">>> + pte |= GEN12_GGTT_PTE_LM;</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + switch (level) {</div>
<div class="ContentPasted0">>> + case I915_CACHE_NONE:</div>
<div class="ContentPasted0">>> + pte |= MTL_GGTT_PTE_PAT1;</div>
<div class="ContentPasted0">>> + break;</div>
<div class="ContentPasted0">>> + case I915_CACHE_LLC:</div>
<div class="ContentPasted0">>> + case I915_CACHE_L3_LLC:</div>
<div class="ContentPasted0">>> + pte |= MTL_GGTT_PTE_PAT0 | MTL_GGTT_PTE_PAT1;</div>
<div class="ContentPasted0">>> + break;</div>
<div class="ContentPasted0">>> + case I915_CACHE_WT:</div>
<div class="ContentPasted0">>> + pte |= MTL_GGTT_PTE_PAT0;</div>
<div class="ContentPasted0">>> + break;</div>
<div class="ContentPasted0">>> + }</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + return pte;</div>
<div class="ContentPasted0">>> +}</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> u64 gen8_ggtt_pte_encode(dma_addr_t addr,</div>
<div class="ContentPasted0">>> enum i915_cache_level level,</div>
<div class="ContentPasted0">>> u32 flags)</div>
<div class="ContentPasted0">>> @@ -247,7 +274,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,</div>
<div class="ContentPasted0">>> gen8_pte_t __iomem *pte =</div>
<div class="ContentPasted0">>> (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> - gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));</div>
<div class="ContentPasted0">>> + gen8_set_pte(pte, ggtt->vm.pte_encode(addr, level, flags));</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> ggtt->invalidate(ggtt);</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> @@ -257,8 +284,8 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,</div>
<div class="ContentPasted0">>> enum i915_cache_level level,</div>
<div class="ContentPasted0">>> u32 flags)</div>
<div class="ContentPasted0">>> {</div>
<div class="ContentPasted0">>> - const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);</div>
<div class="ContentPasted0">>> struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);</div>
<div class="ContentPasted0">>> + const gen8_pte_t pte_encode = ggtt->vm.pte_encode(0, level, flags);</div>
<div class="ContentPasted0">>> gen8_pte_t __iomem *gte;</div>
<div class="ContentPasted0">>> gen8_pte_t __iomem *end;</div>
<div class="ContentPasted0">>> struct sgt_iter iter;</div>
<div class="ContentPasted0">>> @@ -981,7 +1008,10 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)</div>
<div class="ContentPasted0">>> ggtt->vm.vma_ops.bind_vma = intel_ggtt_bind_vma;</div>
<div class="ContentPasted0">>> ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> - ggtt->vm.pte_encode = gen8_ggtt_pte_encode;</div>
<div class="ContentPasted0">>> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))</div>
<div class="ContentPasted0">>> + ggtt->vm.pte_encode = mtl_ggtt_pte_encode;</div>
<div class="ContentPasted0">>> + else</div>
<div class="ContentPasted0">>> + ggtt->vm.pte_encode = gen8_ggtt_pte_encode;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> return ggtt_probe_common(ggtt, size);</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c</div>
<div class="ContentPasted0">>> index 4f436ba7a3c8..1e1b34e22cf5 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c</div>
<div class="ContentPasted0">>> @@ -468,6 +468,25 @@ void gtt_write_workarounds(struct intel_gt *gt)</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +static void mtl_setup_private_ppat(struct intel_uncore *uncore)</div>
<div class="ContentPasted0">>> +{</div>
<div class="ContentPasted0">>> + intel_uncore_write(uncore, GEN12_PAT_INDEX(0),</div>
<div class="ContentPasted0">>> + MTL_PPAT_L4_0_WB);</div>
<div class="ContentPasted0">>> + intel_uncore_write(uncore, GEN12_PAT_INDEX(1),</div>
<div class="ContentPasted0">>> + MTL_PPAT_L4_1_WT);</div>
<div class="ContentPasted0">>> + intel_uncore_write(uncore, GEN12_PAT_INDEX(2),</div>
<div class="ContentPasted0">>> + MTL_PPAT_L4_3_UC);</div>
<div class="ContentPasted0">>> + intel_uncore_write(uncore, GEN12_PAT_INDEX(3),</div>
<div class="ContentPasted0">>> + MTL_PPAT_L4_0_WB | MTL_2_COH_1W);</div>
<div class="ContentPasted0">>> + intel_uncore_write(uncore, GEN12_PAT_INDEX(4),</div>
<div class="ContentPasted0">>> + MTL_PPAT_L4_0_WB | MTL_3_COH_2W);</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> + /*</div>
<div class="ContentPasted0">>> + * Remaining PAT entries are left at the hardware-default</div>
<div class="ContentPasted0">>> + * fully-cached setting</div>
<div class="ContentPasted0">>> + */</div>
<div class="ContentPasted0">>> +}</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> static void tgl_setup_private_ppat(struct intel_uncore *uncore)</div>
<div class="ContentPasted0">>> {</div>
<div class="ContentPasted0">>> /* TGL doesn't support LLC or AGE settings */</div>
<div class="ContentPasted0">>> @@ -603,7 +622,9 @@ void setup_private_pat(struct intel_gt *gt)</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> GEM_BUG_ON(GRAPHICS_VER(i915) < 8);</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))</div>
<div class="ContentPasted0">>> + if (IS_METEORLAKE(i915))</div>
<div class="ContentPasted0">>> + mtl_setup_private_ppat(uncore);</div>
<div class="ContentPasted0">></div>
<div class="ContentPasted0">></div>
<div class="ContentPasted0">> Could you please sync this with DII. We should be programming PAT for</div>
<div class="ContentPasted0">> media tile too.</div>
<div class="ContentPasted0">></div>
<div class="ContentPasted0">> I have refactor this patch in DII along with taking care of media tile</div>
<div class="ContentPasted0">> and I think we should</div>
<div class="ContentPasted0">></div>
<div class="ContentPasted0">> get those changes here too.</div>
<div><br class="ContentPasted0">
</div>
<div class="ContentPasted0">I don't think the PAT index registers are multicasted for MTL. The registers</div>
<div class="ContentPasted0">are at 0x4800 for the render tile and 0x384800 for the media tile, and they</div>
<div class="ContentPasted0">get programmed in gt_init separately when iterating through each gt. No?</div>
<div><br class="ContentPasted0">
</div>
<div class="ContentPasted0">-Fei</div>
<div><br class="ContentPasted0">
</div>
<div class="ContentPasted0">> Regards,</div>
<div class="ContentPasted0">></div>
<div class="ContentPasted0">> Nirmoy</div>
<div class="ContentPasted0">></div>
<div class="ContentPasted0">>> + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))</div>
<div class="ContentPasted0">>> xehp_setup_private_ppat(gt);</div>
<div class="ContentPasted0">>> else if (GRAPHICS_VER(i915) >= 12)</div>
<div class="ContentPasted0">>> tgl_setup_private_ppat(uncore);</div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h</div>
<div class="ContentPasted0">>> index 69ce55f517f5..b632167eaf2e 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h</div>
<div class="ContentPasted0">>> @@ -88,9 +88,18 @@ typedef u64 gen8_pte_t;</div>
<div class="ContentPasted0">>> #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)</div>
<div class="ContentPasted0">>> #define BYT_PTE_WRITEABLE REG_BIT(1)</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +#define GEN12_PPGTT_PTE_PAT3 BIT_ULL(62)</div>
<div class="ContentPasted0">>> #define GEN12_PPGTT_PTE_LM BIT_ULL(11)</div>
<div class="ContentPasted0">>> +#define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7)</div>
<div class="ContentPasted0">>> +#define GEN12_PPGTT_PTE_NC BIT_ULL(5)</div>
<div class="ContentPasted0">>> +#define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4)</div>
<div class="ContentPasted0">>> +#define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3)</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> -#define GEN12_GGTT_PTE_LM BIT_ULL(1)</div>
<div class="ContentPasted0">>> +#define GEN12_GGTT_PTE_LM BIT_ULL(1)</div>
<div class="ContentPasted0">>> +#define MTL_GGTT_PTE_PAT0 BIT_ULL(52)</div>
<div class="ContentPasted0">>> +#define MTL_GGTT_PTE_PAT1 BIT_ULL(53)</div>
<div class="ContentPasted0">>> +#define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12)</div>
<div class="ContentPasted0">>> +#define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52)</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> #define GEN12_PDE_64K BIT(6)</div>
<div class="ContentPasted0">>> #define GEN12_PTE_PS64 BIT(8)</div>
<div class="ContentPasted0">>> @@ -147,6 +156,15 @@ typedef u64 gen8_pte_t;</div>
<div class="ContentPasted0">>> #define GEN8_PDE_IPS_64K BIT(11)</div>
<div class="ContentPasted0">>> #define GEN8_PDE_PS_2M BIT(7)</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)</div>
<div class="ContentPasted0">>> +#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)</div>
<div class="ContentPasted0">>> +#define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)</div>
<div class="ContentPasted0">>> +#define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)</div>
<div class="ContentPasted0">>> +#define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)</div>
<div class="ContentPasted0">>> +#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)</div>
<div class="ContentPasted0">>> +#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)</div>
<div class="ContentPasted0">>> +#define MTL_0_COH_NON REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0)</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> enum i915_cache_level;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> struct drm_i915_gem_object;</div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c</div>
<div class="ContentPasted0">>> index 69b489e8dfed..89570f137b2c 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c</div>
<div class="ContentPasted0">>> @@ -40,6 +40,10 @@ struct drm_i915_mocs_table {</div>
<div class="ContentPasted0">>> #define LE_COS(value) ((value) << 15)</div>
<div class="ContentPasted0">>> #define LE_SSE(value) ((value) << 17)</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */</div>
<div class="ContentPasted0">>> +#define _L4_CACHEABILITY(value) ((value) << 2)</div>
<div class="ContentPasted0">>> +#define IG_PAT(value) ((value) << 8)</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */</div>
<div class="ContentPasted0">>> #define L3_ESC(value) ((value) << 0)</div>
<div class="ContentPasted0">>> #define L3_SCC(value) ((value) << 1)</div>
<div class="ContentPasted0">>> @@ -50,6 +54,7 @@ struct drm_i915_mocs_table {</div>
<div class="ContentPasted0">>> /* Helper defines */</div>
<div class="ContentPasted0">>> #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */</div>
<div class="ContentPasted0">>> #define PVC_NUM_MOCS_ENTRIES 3</div>
<div class="ContentPasted0">>> +#define MTL_NUM_MOCS_ENTRIES 16</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> /* (e)LLC caching options */</div>
<div class="ContentPasted0">>> /*</div>
<div class="ContentPasted0">>> @@ -73,6 +78,12 @@ struct drm_i915_mocs_table {</div>
<div class="ContentPasted0">>> #define L3_2_RESERVED _L3_CACHEABILITY(2)</div>
<div class="ContentPasted0">>> #define L3_3_WB _L3_CACHEABILITY(3)</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +/* L4 caching options */</div>
<div class="ContentPasted0">>> +#define L4_0_WB _L4_CACHEABILITY(0)</div>
<div class="ContentPasted0">>> +#define L4_1_WT _L4_CACHEABILITY(1)</div>
<div class="ContentPasted0">>> +#define L4_2_RESERVED _L4_CACHEABILITY(2)</div>
<div class="ContentPasted0">>> +#define L4_3_UC _L4_CACHEABILITY(3)</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \</div>
<div class="ContentPasted0">>> [__idx] = { \</div>
<div class="ContentPasted0">>> .control_value = __control_value, \</div>
<div class="ContentPasted0">>> @@ -416,6 +427,57 @@ static const struct drm_i915_mocs_entry pvc_mocs_table[] = {</div>
<div class="ContentPasted0">>> MOCS_ENTRY(2, 0, L3_3_WB),</div>
<div class="ContentPasted0">>> };</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> +static const struct drm_i915_mocs_entry mtl_mocs_table[] = {</div>
<div class="ContentPasted0">>> + /* Error - Reserved for Non-Use */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(0,</div>
<div class="ContentPasted0">>> + IG_PAT(0),</div>
<div class="ContentPasted0">>> + L3_LKUP(1) | L3_3_WB),</div>
<div class="ContentPasted0">>> + /* Cached - L3 + L4 */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(1,</div>
<div class="ContentPasted0">>> + IG_PAT(1),</div>
<div class="ContentPasted0">>> + L3_LKUP(1) | L3_3_WB),</div>
<div class="ContentPasted0">>> + /* L4 - GO:L3 */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(2,</div>
<div class="ContentPasted0">>> + IG_PAT(1),</div>
<div class="ContentPasted0">>> + L3_LKUP(1) | L3_1_UC),</div>
<div class="ContentPasted0">>> + /* Uncached - GO:L3 */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(3,</div>
<div class="ContentPasted0">>> + IG_PAT(1) | L4_3_UC,</div>
<div class="ContentPasted0">>> + L3_LKUP(1) | L3_1_UC),</div>
<div class="ContentPasted0">>> + /* L4 - GO:Mem */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(4,</div>
<div class="ContentPasted0">>> + IG_PAT(1),</div>
<div class="ContentPasted0">>> + L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),</div>
<div class="ContentPasted0">>> + /* Uncached - GO:Mem */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(5,</div>
<div class="ContentPasted0">>> + IG_PAT(1) | L4_3_UC,</div>
<div class="ContentPasted0">>> + L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),</div>
<div class="ContentPasted0">>> + /* L4 - L3:NoLKUP; GO:L3 */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(6,</div>
<div class="ContentPasted0">>> + IG_PAT(1),</div>
<div class="ContentPasted0">>> + L3_1_UC),</div>
<div class="ContentPasted0">>> + /* Uncached - L3:NoLKUP; GO:L3 */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(7,</div>
<div class="ContentPasted0">>> + IG_PAT(1) | L4_3_UC,</div>
<div class="ContentPasted0">>> + L3_1_UC),</div>
<div class="ContentPasted0">>> + /* L4 - L3:NoLKUP; GO:Mem */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(8,</div>
<div class="ContentPasted0">>> + IG_PAT(1),</div>
<div class="ContentPasted0">>> + L3_GLBGO(1) | L3_1_UC),</div>
<div class="ContentPasted0">>> + /* Uncached - L3:NoLKUP; GO:Mem */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(9,</div>
<div class="ContentPasted0">>> + IG_PAT(1) | L4_3_UC,</div>
<div class="ContentPasted0">>> + L3_GLBGO(1) | L3_1_UC),</div>
<div class="ContentPasted0">>> + /* Display - L3; L4:WT */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(14,</div>
<div class="ContentPasted0">>> + IG_PAT(1) | L4_1_WT,</div>
<div class="ContentPasted0">>> + L3_LKUP(1) | L3_3_WB),</div>
<div class="ContentPasted0">>> + /* CCS - Non-Displayable */</div>
<div class="ContentPasted0">>> + MOCS_ENTRY(15,</div>
<div class="ContentPasted0">>> + IG_PAT(1),</div>
<div class="ContentPasted0">>> + L3_GLBGO(1) | L3_1_UC),</div>
<div class="ContentPasted0">>> +};</div>
<div class="ContentPasted0">>> +</div>
<div class="ContentPasted0">>> enum {</div>
<div class="ContentPasted0">>> HAS_GLOBAL_MOCS = BIT(0),</div>
<div class="ContentPasted0">>> HAS_ENGINE_MOCS = BIT(1),</div>
<div class="ContentPasted0">>> @@ -445,7 +507,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,</div>
<div class="ContentPasted0">>> memset(table, 0, sizeof(struct drm_i915_mocs_table));</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> table->unused_entries_index = I915_MOCS_PTE;</div>
<div class="ContentPasted0">>> - if (IS_PONTEVECCHIO(i915)) {</div>
<div class="ContentPasted0">>> + if (IS_METEORLAKE(i915)) {</div>
<div class="ContentPasted0">>> + table->size = ARRAY_SIZE(mtl_mocs_table);</div>
<div class="ContentPasted0">>> + table->table = mtl_mocs_table;</div>
<div class="ContentPasted0">>> + table->n_entries = MTL_NUM_MOCS_ENTRIES;</div>
<div class="ContentPasted0">>> + table->uc_index = 9;</div>
<div class="ContentPasted0">>> + table->unused_entries_index = 1;</div>
<div class="ContentPasted0">>> + } else if (IS_PONTEVECCHIO(i915)) {</div>
<div class="ContentPasted0">>> table->size = ARRAY_SIZE(pvc_mocs_table);</div>
<div class="ContentPasted0">>> table->table = pvc_mocs_table;</div>
<div class="ContentPasted0">>> table->n_entries = PVC_NUM_MOCS_ENTRIES;</div>
<div class="ContentPasted0">>> @@ -646,9 +714,9 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)</div>
<div class="ContentPasted0">>> init_l3cc_table(engine->gt, &table);</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> -static u32 global_mocs_offset(void)</div>
<div class="ContentPasted0">>> +static u32 global_mocs_offset(struct intel_gt *gt)</div>
<div class="ContentPasted0">>> {</div>
<div class="ContentPasted0">>> - return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));</div>
<div class="ContentPasted0">>> + return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)) + gt->uncore->gsi_offset;</div>
<div class="ContentPasted0">>> }</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> void intel_set_mocs_index(struct intel_gt *gt)</div>
<div class="ContentPasted0">>> @@ -671,7 +739,7 @@ void intel_mocs_init(struct intel_gt *gt)</div>
<div class="ContentPasted0">>> */</div>
<div class="ContentPasted0">>> flags = get_mocs_settings(gt->i915, &table);</div>
<div class="ContentPasted0">>> if (flags & HAS_GLOBAL_MOCS)</div>
<div class="ContentPasted0">>> - __init_mocs_table(gt->uncore, &table, global_mocs_offset());</div>
<div class="ContentPasted0">>> + __init_mocs_table(gt->uncore, &table, global_mocs_offset(gt));</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> /*</div>
<div class="ContentPasted0">>> * Initialize the L3CC table as part of mocs initalization to make</div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c</div>
<div class="ContentPasted0">>> index ca009a6a13bd..730796346514 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c</div>
<div class="ContentPasted0">>> @@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,</div>
<div class="ContentPasted0">>> return 0;</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))</div>
<div class="ContentPasted0">>> - addr = global_mocs_offset();</div>
<div class="ContentPasted0">>> + addr = global_mocs_offset(rq->engine->gt);</div>
<div class="ContentPasted0">>> else</div>
<div class="ContentPasted0">>> addr = mocs_offset(rq->engine);</div>
<div class="ContentPasted0">>> </div>
<div class="ContentPasted0">>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c</div>
<div class="ContentPasted0">>> index 621730b6551c..480b128499ae 100644</div>
<div class="ContentPasted0">>> --- a/drivers/gpu/drm/i915/i915_pci.c</div>
<div class="ContentPasted0">>> +++ b/drivers/gpu/drm/i915/i915_pci.c</div>
<div class="ContentPasted0">>> @@ -1149,6 +1149,7 @@ static const struct intel_device_info mtl_info = {</div>
<div class="ContentPasted0">>> .has_flat_ccs = 0,</div>
<div class="ContentPasted0">>> .has_gmd_id = 1,</div>
<div class="ContentPasted0">>> .has_guc_deprivilege = 1,</div>
<div class="ContentPasted0">>> + .has_llc = 0,</div>
<div class="ContentPasted0">>> .has_mslice_steering = 0,</div>
<div class="ContentPasted0">>> .has_snoop = 1,</div>
<div class="ContentPasted0">>> .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,</div>
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