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>> On 4/28/23 17:19, Yang, Fei wrote:
<div>>>> On 4/28/23 07:47, fei.yang@intel.com wrote:</div>
<div>>>>> From: Fei Yang <fei.yang@intel.com></div>
<div>>>>></div>
<div>>>>> The first three patches in this series are taken from</div>
<div>>>>> https://patchwork.freedesktop.org/series/116868/</div>
<div>>>>> These patches are included here because the last patch</div>
<div>>>>> has dependency on the pat_index refactor.</div>
<div>>>>></div>
<div>>>>> This series is focusing on uAPI changes,</div>
<div>>>>> 1. end support for set caching ioctl [PATCH 4/5]</div>
<div>>>>> 2. add set_pat extension for gem_create [PATCH 5/5]</div>
<div>>>>></div>
<div>>>>> v2: drop one patch that was merged separately</div>
<div>>>>> 341ad0e8e254 drm/i915/mtl: Add PTE encode function</div>
<div>>>>> v3: rebase on https://patchwork.freedesktop.org/series/117082/</div>
<div>>>></div>
<div>>>> Hi, Fei.</div>
<div>>>></div>
<div>>>> Does this uAPI update also affect any discrete GPUs supported by i915,</div>
<div>>></div>
<div>>> It does.</div>
<div>>></div>
<div>>>> And in that case, does it allow setting non-snooping PAT indices on</div>
<div>>>> those devices?</div>
<div>>></div>
<div>>> It allows setting PAT indices specified in</div>
<div>>> KMD does a sanity check so that it won't go over the max recommended</div>
<div>>> by bspec.</div>
<div>>></div>
<div>>>> If so, since the uAPI for discrete GPU devices doesn't allow incoherency</div>
<div>>>> between GPU and CPU (apart from write-combining buffering), the correct</div>
<div>>>> CPU caching mode matching the PAT index needs to be selected for the</div>
<div>>>> buffer object in i915_ttm_select_tt_caching().</div>
<div>>></div>
<div>>> The patch doesn't affect the CPU caching mode setting logic though.</div>
<div>>> And the caching settings for objects created by kernel should remain</div>
<div>>> the same for both CPU and GPU, objects created by userspace are</div>
<div>>> managed completely by userspace.</div>
<div>>></div>
<div class="elementToProof">>> One question though, what do you mean by non-snooping PAT indices?</div>
<div class="elementToProof ContentPasted0">>
<div class="ContentPasted0">> Yes, that was actually the bottom question: What do these PAT settings</div>
<div class="ContentPasted0">> allow you to do WRT the snooping on supported discrete devices (DG2) on</div>
<div class="ContentPasted0">> i915?</div>
<div class="ContentPasted0">> If they indeed don't allow disabling snooping, then that's not a problem.</div>
<div><br class="ContentPasted0">
</div>
<div class="ContentPasted0">When dGPU's access SysMem, the PCIe default is for that access to snoop the</div>
<div class="ContentPasted0">host's caches. All of our current dGPU's do that -- independent of PAT setting.</div>
<div><br class="ContentPasted0">
</div>
<div class="ContentPasted0">> If they do, the ttm code there needs some modification.</div>
<div><br class="ContentPasted0">
</div>
<div class="ContentPasted0">I'm not familiar with ttm, but if your concern is that certain PAT index</div>
<div class="ContentPasted0">could disable snooping, that is not possible for current dGPU's.</div>
<div class="ContentPasted0">I think it is possible for Xe2/3 though, because there will be COH_MODE</div>
<div class="ContentPasted0">defined in the PAT registers going forward.</div>
<div><br class="ContentPasted0">
</div>
<div class="ContentPasted0">-Fei</div>
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