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<div class="moz-cite-prefix">On 6/26/2024 01:56, Gustavo Sousa
wrote:<br>
</div>
<blockquote type="cite" cite="mid:20240625202652.315936-1-gustavo.sousa@intel.com">
<pre class="moz-quote-pre" wrap="">Starting with Xe_LPDP, support for Type-C connections is provided by
PICA and programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable
anymore. Those registers don't even exist in recent display IPs. As
such, skip programming them.
Bspec: 65750, 65448</pre>
</blockquote>
I guess, we can add the Bspec page (49190) of the last platform
which contained the reg <span style="white-space: pre-wrap">DFLEXDPMLE, so as to have a better diff view for someone reviewing. </span>
<blockquote type="cite" cite="mid:20240625202652.315936-1-gustavo.sousa@intel.com">
<pre class="moz-quote-pre" wrap="">
Signed-off-by: Gustavo Sousa <a class="moz-txt-link-rfc2396E" href="mailto:gustavo.sousa@intel.com"><gustavo.sousa@intel.com></a></pre>
</blockquote>
With above comments, <span style="white-space: pre-wrap">LGTM and
Reviewed-by: Shekhar Chauhan <a class="moz-txt-link-rfc2396E" href="mailto:shekhar.chauhan@intel.com"><shekhar.chauhan@intel.com></a>
</span>
<blockquote type="cite" cite="mid:20240625202652.315936-1-gustavo.sousa@intel.com">
<pre class="moz-quote-pre" wrap="">
---
drivers/gpu/drm/i915/display/intel_tc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 9887967b2ca5..6f2ee7dbc43b 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -393,6 +393,9 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
u32 val;
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
drm_WARN_ON(&i915->drm,
lane_reversal && tc->mode != TC_PORT_LEGACY);
</pre>
</blockquote>
<pre class="moz-signature" cols="72">--
-shekhar</pre>
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